Parallel solving of layout optimization

A system comprising:

• at least one computing device configured to optimize an integrated circuit layout for implementation in an integrated circuit by performing actions including:
• obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout;
• partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules;
• determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists;
• creating a plurality of integer linear programming problems associated with each of the groups;
• determining a solution for each of the plurality of integer linear programming problems;
• and
• integrating each solution together to form a second integrated circuit layout.

A computer program product comprising program code embodied in at least one non-transitory computer-readable medium, which when executed, enables a computer system to optimize an integrated circuit layout for implementation in an integrated circuit by performing actions comprising:

• obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout;
• partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules;
• determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists;
• creating a plurality of integer linear programming problems associated with each of the groups;
• determining a solution for each of the plurality of integer linear programming problems;
• and
• integrating each solution together to form a second integrated circuit layout.