Tool for glitch removal
AssigneeIntel Corporation
InventorsNicholas Denler, Iredamola Dammy Olopade, Sunil Gupta, Sulakshana Shyama Nath
Life of this patent
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Abstract
Embodiments of an electronic design automation system are generally described herein. In some embodiments, glitch-sensitive nodes in an integrated circuit design are identified. For each glitch-sensitive node, a circuit fanin cone is analyzed to look for circuit structures that can produce glitches. The integrated circuit design can be simulated and modified if the simulation indicates that a glitch would occur in the integrated circuit design.
Claims15
At least one non-transistory machine readable medium comprising a plurality of instructions that in response to being executed on a computing device, cause the computing device to:
- identify a glitch-sensitive node in an integrated circuit design;
- add a logical attribute to the glitch-sensitive node included in an electronic design tool database;
- in response to identifying the glitch-sensitive node, analyze a circuit fanin cone of the glitch-sensitive node to look for circuit structures that can produce glitches that could propagate to the glitch-sensitive node;
- simulate the integrated circuit design in a register transfer language (RTL) view to determine when a glitch would occur in the integrated circuit design;
- and
- modify the fanin cone of the glitch-sensitive node so that the fanin cone does not contain, structures that can produce glitches when the simulation indicates that a glitch would occur in the integrated circuit design.
At least one non-transistory machine readable medium comprising a plurality of instructions that in response to being executed on a computing device, cause the computing device to:
- mark nodes in an integrated circuit design as glitch-sensitive nodes;
- simulate the integrated circuit design;
- and
- analyze a fanin cone for each glitch-sensitive node to look for circuit structures that can produce glitches and, for each glitch-sensitive node, to modify the fanin cone of the glitch- sensitive node so that the fanin cone does not contain structures that can produce glitches when a simulation of the integrated circuit design indicates that a glitch would occur in the integrated circuit design.
At least one non-transistory machine readable medium comprising a plurality of instructions that in response to being executed on a computing device, cause the computing device to:
- mark nodes in an integrated circuit design that are glitch-sensitive nodes;
- identify circuit structures that can produce glitches that could propagate to one of the glitch-sensitive nodes;
- simulate the integrated circuit design;
- and
- for each glitch-sensitive node, modify a fanin cone of the glitch-sensitive node so that the fanin cone does not contain structures that can produce glitches when the simulation indicates that a glitch would occur in the integrated circuit design.
Dependencies are inferred from the claim text.