Statistical corner evaluation for complex on chip variation model

A computer-implemented method of statistical static timing analysis (SSTA) comprising:

• receiving, by a computer, information describing a circuit, the information comprising:
• an input node and an output node, such that there is a path from the input node to the output node,
• the path comprising a plurality of cells comprising a first cell, each cell having a parametric delay represented as a nominal delay value and a standard deviation value, the standard deviation value representing a timing impact of local random variation;
• and
• performing statistical static timing analysis (SSTA) based on on-chip variation (OCV) model, the SSTA comprising, determining a specific delay shift value for the first cell under which a corner slack is reached as a ratio of the magnitude of standard deviation value for the first cell and a square root of the sum of squares of the standard deviation values of cells along the path.

A non-transitory computer readable storage medium storing computer program modules configured to execute on a computer processor, the computer program modules configured to:

• receive information describing a circuit, the information comprising:
• an input node and an output node, such that there is a path from the input node to the output node,
• the path comprising a plurality of cells comprising a first cell, each cell having a parametric delay represented as a nominal delay value and a standard deviation value, the standard deviation value representing a timing impact of local random variation;
• and
• perform statistical static timing analysis (SSTA) based on on-chip variation (OCV) model, the SSTA comprising, determining a specific delay shift value for the first cell under which a corner slack is reached as a ratio of the magnitude of standard deviation value for the first cell and a square root of the sum of squares of the standard deviation values of cells along the path.

A system for performing statistical static timing analysis (SSTA) based on on-chip variation (OCV) model, the SSTA comprising:

• a computer processor;
• and
• a computer-readable storage medium storing computer program modules configured to execute on the computer processor, the computer program modules configured to:
• receive information describing a circuit, the information comprising:
• an input node and an output node, such that there is a path from the input node to the output node,
• the path comprising a plurality of cells comprising a first cell, each cell having a parametric delay represented as a nominal delay value and a standard deviation value, the standard deviation value representing a timing impact of local random variation;
• and
• perform statistical static timing analysis (SSTA) based on on-chip variation (OCV) model, the SSTA comprising, determining a specific delay shift value for the first cell under which a corner slack is reached as a ratio of the magnitude of standard deviation value for the first cell and a square root of the sum of squares of the standard deviation values of cells along the path.