US 8,555,221 B2 · Partitioning for hardware-accelerated functional verification

Abstract

A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Claims14

Dependent claims

A computer-implemented method of partitioning a circuit design for hardware-accelerated functional verification, comprising:

receiving a description of the circuit design which includes a plurality of nodes interconnected to form a plurality of nets, by executing first program instructions in a computer system;
constructing a directed hypergraph with vertices representing the nodes and edges representing the nets, one of the vertices in each edge being a source, by executing second program instructions in the computer system;
computing a slack for each edge based on the edge's source, by executing third program instructions in the computer system;
assigning each edge a weight which is a function of the edge's slack, by executing fourth program instructions in the computer system;
partitioning the hypergraph to create a vertex partitionment which optimizes a total weighted cut of the edges using the edge weights, by executing fifth program instructions in the computer system;
and
mapping the vertex partitionment to a partitionment of the nodes, by executing sixth program instructions in the computer system.

4 more elements

Dependencies are inferred from the claim text.

Partitioning for hardware-accelerated functional verification

Life of this patent

Partitioning for hardware-accelerated functional verification

Life of this patent

Abstract

Claims14