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US 8,555,131 B2Granted
Techniques to control power consumption in an iterative decoder by control of node configurations
AssigneeSilicon Laboratories Inc.
InventorsDavid Rault, Olivier Souloumiac
Life of this patent
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Abstract
A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include progressively enabling and disabling nodes of the iterative decoder to perform iterative decoding on a demodulated signal to provide a decoded signal with minimal variation of a supply voltage.
Claims22
An apparatus comprising:
- an iterative decoder including:
- a plurality of variable node processors each to receive a channel input and at least one of a plurality of check node values and to calculate a variable node value;
- a variable node memory including a plurality of nodes each associated with one of the variable node processors;
- a shuffle unit coupled to receive a variable node value from each of the plurality of variable node processors and to provide the variable node value to at least one of a plurality of check node processors coupled to the shuffle unit;
- the plurality of check node processors each to receive at least one variable node value and to calculate a check node value including a parity value and a magnitude value;
- a check node memory including a plurality of nodes each associated with one of the check node processors;
- and
- a controller coupled to the plurality of variable node processors, the variable node memory, the plurality of check node processors, the check node memory, and the shuffle unit, the controller to progressively enable a target number of the check node processors from a time prior to a start of iterative decoding of a frame and progressively disable the target number of the check node processors after successful decoding of the frame.
5 more elements
A method comprising:
- performing iterative decoding on first non-relevant data in an iterative decoder prior to availability of a demodulated signal for iterative decoding, the iterative decoder having a plurality of nodes each including a variable node processor and a check node processor, wherein a progressive number of the plurality of nodes are enabled during the iterative decoding on the non-relevant data;
- performing iterative decoding on the demodulated signal in the iterative decoder to provide a decoded signal, using a target number of the plurality of nodes;
- and
- thereafter performing iterative decoding on second non-relevant data in the iterative decoder, wherein a regressive number of the plurality of nodes are enabled during the iterative decoding on the non-relevant data.
1 more element
A system comprising:
- a receiver to receive radio frequency (RF) signals and to downconvert the received RF signal to a baseband signal and demodulate the baseband signal into a demodulated signal, the receiver having a forward error correction (FEC) circuit including an iterative decoder to decode the demodulated signal into a decoded signal and a controller coupled to the iterative decoder to progressively enable or disable each of a plurality of nodes of the iterative decoder during iterative decoding of the demodulated signal to reduce variation of a supply voltage provided to the iterative decoder from a power supply, each of the plurality of nodes including a variable node processor and a check node processor, a variable node memory portion and a check node memory portion.
Dependencies are inferred from the claim text.