Self-timed error correcting code evaluation system and method
AssigneeMicron Technology, Inc.
InventorJames B. Johnson
Life of this patent
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Abstract
Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.
Claims20
In a memory system, a method of evaluating signals, comprising:
- receiving a plurality of signals;
- decoding a command from command signals of the received signals;
- receiving signals corresponding to a transmitted error correcting code;
- calculating a part of a generated error correcting code from at least some of the received signals;
- completing the calculation of the generated error correcting code from the calculated part of the error correcting code;
- comparing the calculated error correcting code with the transmitted error correcting code;
- providing the command to error correcting code logic responsive to a clock signal;
- and
- if the calculated error correcting code matches the transmitted error correcting code, providing a valid signal to the error correcting code logic at a different time than the command to output the command asynchronously with any clock signal as the comparison is completed.
A logic path for accessing a memory array within a memory device, comprising:
- a first input configured to receive signals corresponding to a transmitted error correcting code;
- a static logic circuit coupled to the input, the static logic circuit configured to calculate a part of a generated error correcting code from at least some of the received signals, wherein the calculation for the part of the generated error correcting code is asynchronous with any clock signal as the received signals are received;
- and
- a dynamic logic circuit coupled to the static logic circuit, the dynamic logic circuit configured to receive the part of the generated error correcting code and to calculate the generated error correcting code from the part of the generated error correcting code, the dynamic logic circuit further configured to compare the generated error correcting code with the transmitted error correcting code, and the dynamic logic circuit further configured to responsive to completion of the comparison and asynchronous to a clock signal, provide a valid signal conditioned upon the generated error correcting code matching the transmitted error correcting code.
A method, comprising:
- receiving data and a first error correcting code at a logic path;
- calculating a partial sum of terms based on the data;
- calculating a second error correcting code based on the partial sum of terms;
- comparing the second error correcting code with the first error correcting code;
- and
- responsive to completion of the comparison, providing, to an error correcting code valid gate of the logic path without intermediate latching, a validity signal having a valid value conditioned upon the second error correcting code matching the first error correcting code.
Dependencies are inferred from the claim text.