Apparatus and method for detecting an approaching error condition

Sequential storage circuitry configured as a second sequential storage structure within a data processing apparatus, the data processing apparatus having combinatorial circuitry configured to receive at least one input signal and to perform a processing operation to generate an output signal, a first sequential storage structure, controlled by a first clock signal, and configured to provide said at least one input signal to the combinatorial circuitry, and the second sequential storage structure, controlled by a second clock signal, and configured to latch the output signal generated by the combinatorial circuitry, the sequential storage circuitry comprising:

• a main storage element configured to latch a value of the output signal from said combinatorial circuitry and to provide said value of the output signal to a subsequent combinatorial circuitry;
• and
• transition detection circuitry configured to detect a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct;
• the sequential storage circuitry is configured to operated in one of a first mode of operation and a second mode of operation, wherein;
• in said first mode of operation, the predetermined timing window is a timing window ahead of a time at which the main storage element latches said value of the output signal such that the approaching error condition detected by the transition detection circuitry is an approaching setup timing error due to a propagation delay within the combinatorial circuitry producing said output signal;
• and
• in said second mode of operation, the predetermined timing window is a timing window after said time at which the main storage element latches said value of the output signal such that the approaching error condition detected by the transition detection circuitry is an approaching hold timing error due to an increase in a skew between the first and second clock signals.

A method of operating a data processing apparatus having combinatorial circuitry configured to receive at least one input signal and performing a processing operation to generate an output signal, a first sequential storage structure controlled by a first clock signal to provide said at least one input signal to the combinatorial circuitry, and a second sequential storage structure controlled by a second clock signal to latch the output signal generated by the combinatorial circuitry, the method comprising the steps of:

• latching, within a main storage element of the second sequential storage structure, a value of the output signal for provision to a subsequent combinatorial circuitry;
• detecting a change of the value of the output signal latched by the main storage element during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element is still correct;
• and
• operating the second sequential storage structure in one of a first mode of operation and a second mode of operation, wherein
• in said first mode of operation, the predetermined timing window is a timing window ahead of a time at which the main storage element latches said value of the output signal such that the approaching error condition detected by said detecting step is an approaching setup timing error due to a propagation delay within the combinatorial circuitry;
• and
• in said second mode of operation, the predetermined timing window is a timing window after said time at which the main storage element latches said value of the output signal such that the approaching error condition detected by said detecting step is an approaching hold timing error due to an increase in a skew between the first and second clock signals,
• wherein:
• during said step of detecting a change, employing a shadow storage element to latch a value of the output signal at a timing different to the main storage element, and employing state difference detection circuitry to determine, from a difference in the values latched by the main storage element and the shadow storage element, said approaching error condition whilst the value stored in the main storage element is still correct, wherein;
• in said first mode of operation, the shadow storage element is operated by the second clock signal and the main storage element is operated by a delayed version of the second dock signal, to cause the shadow storage element to operate ahead of the main storage element such that the approaching error condition detected by the state difference detection circuitry is said approaching setup timing error due to a propagation delay within the combinatorial circuitry;
• and
• in said second mode of operation, the main storage element is operated by the second clock signal and the shadow storage element is operated by the delayed version of the second clock signal, to cause the main storage element to operate ahead of the shadow storage element such that the approaching error condition detected by the state difference detection circuitry is said approaching hold timing error due to an increase in a skew between the first and second clock signals.

A data processing apparatus comprising:

• combinatorial means for receiving at least one input signal and for performing a processing operation to generate an output signal;
• a first sequential storage means, controlled by a first clock signal, for providing said at least one input signal to the combinatorial means;
• a second sequential storage means, controlled by a second clock signal, for latching the output signal generated by the combinatorial means;
• the second sequential storage means comprising a main storage element means for latching a value of the output signal and for providing said value of the output signal to a subsequent combinatorial means, and transition detection means for detecting a change of the value of the output signal latched by the main storage element means during a predetermined timing window, said change indicating an approaching error condition whilst the value stored in the main storage element means is still correct;
• the second sequential storage means for operating in one of a first mode of operation and a second mode of operation;
• in said first mode of operation, the predetermined timing window being a timing window ahead of a time at which the main storage element means latches said value of the output signal such that the approaching error condition detected by the transition detection means is an approaching setup timing error due to a propagation delay within the combinatorial means;
• and
• in said second mode of operation, the predetermined timing window being a timing window after said time at which the main storage element means latches said value of the output signal such that the approaching error condition detected by the transition detection means is an approaching hold timing error due to an increase in a skew between the first and second clock signals wherein:
• the transition detection means of the second sequential storage means comprises a shadow storage element means for latching a value of the output signal at a timing different to the main storage element means, and state difference detection means for determining, from a difference in the values latched by the main storage element means and the shadow storage element means, said approaching error condition whilst the value stored in the main storage element means is still correct, wherein;
• in said first mode of operation, the shadow storage element means is operated by the second clock signal and the main storage element means is operated by a delayed version of the second clock signal, to cause the shadow storage element means to operate ahead of the main storage element means such that the approaching error condition detected by the state difference detection means is said approaching setup timing error due to a propagation delay within the combinatorial means;
• and
• in said second mode of operation, the main storage element means is operated by the second clock signal and the shadow storage element means is operated by the delayed version of the second clock signal, to cause the main storage element means to operate ahead of the shadow storage element means such that the approaching error condition detected by the state difference detection means is said approaching hold timing error due to an increase in a skew between the first and second clock signals.