Test device and method for the SoC test architecture
AssigneeIndustrial Technology Research Institute
InventorsMing-Hsueh Wu, Kun-Lun Luo
Life of this patent
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Abstract
A test device for an SoC test architecture has a test input port, a test output port, a plurality of cores, a register, and a plurality of user defined logics. The register has a plurality of bits corresponding to the cores. Each of the user defined logics is connected to a corresponding bit of the register and a corresponding one of the cores. Each of the user defined logic receives a plurality of test control signals, and receives the corresponding bit of the register to change values of the test control signals. Outputs of each of the user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated.
Claims11
A test device for the SoC test architecture, comprising:
- m cores, wherein m is an integer, and i is an integer between 1 and m−1, wherein test outputs of a first core are serial-connected to test inputs of a second core, and test outputs of an ith core of the m cores are serial-connected to test inputs of an (i+1)th core of the m cores;
- a test input port, wherein the test input port is serial-connected to test inputs of the first core of the m cores;
- a test output port, wherein the test output port is serial-connected to test outputs of an mth core of the m cores;
- a register, comprising m bits corresponding to the m cores;
- and
- m user defined logics, each connected to a corresponding bit of the register and a corresponding one of the m cores, receiving a plurality of test control signals, receiving the corresponding bit of the register to change values of test control signals and outputting the changed test control signals, wherein the changed test control signals of each of the m user defined logics are connected to the corresponding core to determine whether a test instruction of the corresponding core is or is not needed to be updated;
- wherein in each of the m cores which are selected to change the test instructions by the changed test control signals, the test instruction is shifted from the test input to a wrapper instruction register;
- wherein in each of the m cores which are not selected to change the test instructions by the changed test control signals, test data is shifted from the test input to the test output through a bypass register.
A test device for the SoC test architecture, comprising:
- m cores, wherein m is an integer, and i is an integer between 1 and m−1, whereis test outputs of a first core are serial-connected to test inputs of a second core, and test outputs of an ith core of the m cores are serial connected to test inputs of an (i+1)th core of the m cores;
- a test input port, wherein the test input port is serial-connected to test inputs of the first core of the m cores;
- a test output port, wherein the test output port is serial-connected to test outputs of an mth core of the m cores;
- and
- a register, comprising m bits corresponding to the m cores, wherein each of the m cores comprises an user defined logic connected to a corresponding bit of the register, and receives a plurality of test control signals and the corresponding bit of the register, and changes values of the test control signals according to the corresponding bit of the register to determine whether a test instruction of the each core is or is not needed to be updated;
- wherein in each of the m cores which are selected to change the test instructions by the changed test control signal, the test instruction is shifted from the test input to a wrapper instruction register;
- wherein in each of the m cores which are not selected to change the test instructions by the changed test control signal, test data is shifted from the test input to the test output through a bypass register.
Dependencies are inferred from the claim text.