Target device providing debugging function and test system comprising the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunsun Ahn, Jaegon Lee
Life of this patent
Estimating the term…
Abstract
A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode.
Claims18
A test system for debugging a target device, comprising:
- a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode,
- wherein the switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode,
- wherein the first IP block includes at least one processor, the first IP block being configured not to be powered while the second IP block configured to be powered at the power saving mode,
- wherein the first IP block is configured to perform a debugging operation at the normal mode and not to perform a debugging operation at the power saving mode, and wherein the second IP block is configured to perform a debugging operation at the power saving mode.
A target device for supporting a debug function, comprising:
- a processor block including at least one processor, the processor block being configured to be powered at a normal mode to support a debugging operation;
- an alive block configured to be powered at a power saving mode to support a debugging operation;
- and
- a switch block configured to form a first signal transfer path into the processor block at the normal mode and to form a second signal transfer path into the alive block at the power saving mode,
- wherein the processor block is not powered at the power saving mode,
- wherein the processor block is configured to perform a debugging operation at the normal mode and not to perform a debugging operation at the power saving mode, and
- wherein the alive block is configured to perform a debugging operation at the power saving mode.
Dependencies are inferred from the claim text.