Memory error detection
AssigneeRambus Inc.
InventorsIan Shaeffer, Craig E. Hampel
Life of this patent
Estimating the term…
Abstract
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
Claims28
A first integrated circuit, comprising:
- at least one transmitter operable to transmit, in association with a command, data and an associated address to a second integrated circuit;
- and
- a receiver operable to receive information from the second integrated circuit, the information indicating error if present in the data as received by the second integrated circuit and indicating error if present in the associated address as received by the second integrated circuit;
- wherein the first integrated circuit is operable to distinguish error in the data from error in the associated address, and is operable to take a first remedial action in the event of error in the data and a second remedial action in the event of error in the associated address.
A first integrated circuit, comprising:
- at least one transmitter operable to transmit data associated with a command and an associated address to a second integrated circuit;
- and
- a receiver operable to receive information from the second integrated circuit indicating error in the data and indicating error in the associated address;
- circuitry operable to take a first remedial action in the event of an error in the data;
- and
- circuitry operable to take a second remedial action in the event of an error in the associated address.
A memory controller integrated circuit, comprising:
- at least one transmitter operable to transmit write data to a memory device;
- at least one transmitter operable to transmit address information corresponding to the write data to the memory device;
- a receiver operable to receive information representing error in the write data and information representing error in the address information from the memory device;
- circuitry operable to take a first remedial action in the event of an error in transmitted data and to take a second remedial action in the event of an error in transmitted address information.
A first integrated circuit, comprising:
- at least one transmitter operable to transmit data associated with a command and an associated address to a second integrated circuit;
- and
- a receiver operable to receive information from the second integrated circuit indicating error in the data and indicating error in the associated address;
- means for taking first remedial action in the event of an error in the data and second remedial action in the event of an error in the associated address.
Dependencies are inferred from the claim text.