Frequency adapter utilized in high-speed internal buses
AssigneeBroadcom Corporation
InventorsAsaf Koren, David Avishai, Limor Yonatani, Yariv Aviram, Jacob Harel
Life of this patent
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Abstract
A frequency adapter for synchronizing data transfers between a low-frequency module and a high-frequency module connected to an internal bus. The frequency adapter includes a low-to-high synchronization unit for synchronizing data transfers from the low frequency module to the high-frequency module, wherein the low-to-high synchronization unit is clocked by a low frequency clock; and a high-to-low synchronization unit for synchronizing data transfers from the high frequency module to the low-frequency module, wherein the high-to-low synchronization unit is clocked by a low frequency clock.
Claims18
A frequency adapter for synchronizing data transfers between a low-frequency module configured to operate at a first frequency and a high-frequency module configured to operate at a second frequency, the second frequency being higher than the first frequency, comprising:
- a low-to-high frequency synchronization unit configured to receive a plurality of data bursts from the low-frequency module, each of the plurality of data bursts including a plurality of data packets, to store the plurality of data packets in a buffer, and to provide a signal indicative of whether the buffer is empty;
- an end of burst (EOB) unit configured to track a number of the plurality of data bursts stored in the buffer and to provide an EOB-enabled signal when the number is greater than zero;
- a first logic device configured to provide a valid fast signal based on the signal and the EOB-enabled signal;
- and
- a second logic device configured to provide a POP signal based on the valid fast signal and an acknowledgement (ACK) signal, the ACK signal being indicative that the high-frequency module is ready to receive data,
- wherein the low-to-high frequency synchronization unit is further configured to transfer the plurality of data packets from the buffer to the high-frequency module based on the POP signal.
In an integrated circuit, a method for synchronizing data between a first module and a second module operating at different frequencies, comprising:
- receiving a plurality of data bursts from the first module, each of the plurality of data bursts including a plurality of data packets;
- storing the plurality of data packets in a buffer;
- generating a signal indicative of whether the buffer is empty;
- tracking a number of the plurality of data bursts stored in the buffer;
- generating an end-of-burst (EOB)-enabled signal when the number is greater than zero;
- generating a valid fast signal based on a first logical AND operation of the signal and the EOB-enabled signal;
- generating a POP signal based on a second logical AND operation of the valid fast signal and an acknowledgement (ACK) signal, the ACK signal being indicative that the second module is ready to receive data;
- and
- transferring the plurality of data packets from the buffer to the second module based on the POP signal, the signal, and the EOB-enabled signal.
A frequency adapter for synchronizing data transfers between a first module and a second module operating at different frequencies, comprising:
- a first frequency synchronization unit configured to receive a data burst from the first frequency module, the data burst including a plurality of data packets, and to store the plurality of data packets in a buffer;
- a second frequency synchronization unit configured to transfer another plurality of data packets from the second module to the first module based on an acknowledgement (ACK) signal, the ACK signal being indicative that the first module is ready to receive the another plurality of data packets;
- and
- an end of burst (EOB) unit configured to track a number of the plurality of data bursts stored in the buffer and to assert an EOB-enabled signal when the number is greater than zero,
- wherein the first frequency synchronization unit is further configured to assert a signal when the buffer is not empty and to transfer the plurality of data packets to the second module when the signal and the EOB-enabled signal are asserted and the second module is ready to receive the plurality of data packets.
Dependencies are inferred from the claim text.