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US 8,555,041 B2Granted
Method for performing a return operation in parallel with setting status flags based on a return value register test
AssigneeAtmel Corporation
InventorsErik K. Renno, Oyvind Strom, Morten W. Lund
Life of this patent
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Abstract
Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting status flags. Testing the content of the return value register and setting the status flags are performed in response to a single instruction.
Claims16
A method comprising:
- receiving a single instruction that includes a return operation;
- dividing the single instruction into a first micro-operation and a second micro-operation in an instruction decode stage, wherein the first micro-operation is configured for performing the return operation and the second micro-operation is configured for performing a test operation;
- reading, using the first micro-operation, information associated with a return address from a register file in the instruction decode stage;
- providing, using the first micro-operation, the information associated with the return address to an arithmetic logic unit in an execution stage;
- reading, using the second micro-operation in the instruction decode stage in parallel with the first micro-operation in the execution stage, a content of a return value register;
- responsive to the reading using the second micro-operation in the instruction decode stage, testing the content of the return value register using the second micro-operation in the execution stage;
- setting, using the second micro-operation in the execution stage, status flags that includes writing a value into a flag register based on testing the content of the return value register;
- and
- providing, while the first micro-operation is in a memory stage in parallel with the second micro-operation in the execution stage, the information associated with the return address to a pipeline register connected to a multiplexer included in a writeback stage, the multiplexer configured for sending the information associated with the return address to a program counter via an output of the multiplexer.
6 more elements
A processing unit comprising:
- a program counter, wherein the processing unit is configured to execute a single instruction that includes a return operation and is divided into a first micro-operation and a second micro-operation in an instruction decode stage, wherein:
- the first micro-operation is configured to return information associated with a return address and provide, based on execution of the first micro-operation in a memory stage, the information to a multiplexer included in a writeback stage;
- and
- the second micro-operation is configured to test, in an execution stage in parallel with the first micro-operation in the memory stage, a content of a return value register and set status flags including writing a value into a flag register based on testing the content of the return value register;
- and
- the multiplexer configured to send the information associated with the return address to a program counter via an output of the multiplexer.
3 more elements
A non-transitory processor-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform operations including:
- receiving a single instruction that includes a return operation;
- dividing the single instruction into a first micro-operation and a second micro-operation in an instruction decode stage, wherein the first micro-operation is configured for performing the return operation and the second micro-operation is configured for performing a test operation;
- reading, using the first micro-operation, information associated with a return address from a register file in the instruction decode stage;
- providing, using the first micro-operation, the information associated with the return address to an arithmetic logic unit in an execution stage;
- reading, using the second micro-operation in the instruction decode stage in parallel with the first micro-operation in the execution stage, a content of a return value register;
- responsive to the reading using the second micro-operation in the instruction decode stage, testing the content of the return value register using the second micro-operation in the execution stage;
- setting, using the second micro-operation in the execution stage, status flags that includes writing a value into a flag register based on testing the content of the return value register;
- and
- providing, while the first micro-operation is in a memory stage in parallel with the second micro-operation in the execution stage, the information associated with the return address to a pipeline register connected to a multiplexer included in a writeback stage, the multiplexer configured for sending the information associated with the return address to a program counter via an output of the multiplexer.
6 more elements
Dependencies are inferred from the claim text.