Indirect branch target predictor that prevents speculation if mispredict is expected

A processor comprising:

• an instruction cache configured to store a plurality of instructions including indirect branch instructions;
• and
• a fetch control unit coupled to the instruction cache and configured to generate fetch addresses to fetch instructions from the instruction cache, wherein the fetch control unit comprises an indirect branch target predictor configured to predict target addresses for indirect branch instructions, and wherein the fetch control unit is configured to use the predicted target address if an indirect branch instruction is in a speculative instruction stream, and wherein the indirect branch instruction comprises one or more register operands used by the processor during execution to calculate the target address, and wherein the indirect branch target predictor is configured to store a plurality of indirect branch target addresses and a corresponding plurality of validation values generated from state corresponding to previously-executed indirect branch instructions that generated the plurality of indirect branch target addresses during execution, and wherein the state comprises one or more register addresses of the one or more register operands, and wherein the indirect branch predictor is coupled to receive corresponding data for the indirect branch instruction in the speculative instruction stream, and wherein the indirect branch predictor is configured not to predict a first target address selected from the plurality of indirect branch target addresses for the indirect branch instruction responsive to the corresponding data not matching a first validation value associated with the first target address.

A method comprising:

• receiving data corresponding to an indirect branch instruction in an indirect branch target predictor;
• the indirect branch target predictor selecting a branch predictor entry in the indirect branch target predictor, wherein the branch predictor entry stores a target address and a validation tag;
• the indirect branch target predictor comparing the validation tag to the data;
• inhibiting a prediction of the target address for the indirect branch instruction responsive to the validation tag not matching the data;
• and
• inhibiting processing of instructions at a sequential address to the indirect branch instruction responsive to the validation tag not matching the data.