System and method for using a local condition code register for accelerating conditional instruction execution in a pipeline processor
AssigneeQUALCOMM Incorporated
InventorBohuslav Rychlik
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AssigneeQUALCOMM Incorporated
InventorBohuslav Rychlik
Estimating the term…
A method of executing a conditional instruction within a pipeline processor having a plurality of pipelines, the processor having a first condition code register associated with a first pipeline and a second condition code register associated with a second pipeline is disclosed. The method saves a most recent condition code value to either the first condition code register or the second condition code register. The method further sets an indicator indicating whether the second condition code register has the most recent condition code value and retrieves the most recent condition code value from either the first or second condition code register based on the indicator. The method uses the most recent condition code value to determine if the conditional instruction should be executed.
A method of executing a conditional instruction within a pipeline processor having multiple pipelines, the pipeline processor having a first condition code register associated with a first pipeline and a second condition code register associated with a second pipeline, the method comprising:
A pipeline processor comprising:
A pipeline processor comprising:
A non-transitory computer-readable medium including program code that, when executed by a processor, causes the processor to:
Dependencies are inferred from the claim text.