Conflict-free register allocation using a multi-bank register file with input operand alignment
AssigneeNVIDIA Corporation
InventorsAnjul Patney, William J. Dally
Life of this patent
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AssigneeNVIDIA Corporation
InventorsAnjul Patney, William J. Dally
Estimating the term…
One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions. Each function unit input may be directly connected to one bank of the multi-bank register file with neither a switch nor a staging register. A compiler or register allocation unit ensures that the register file accesses for each instruction are conflict-free (no instruction can access the same bank more than once in the same cycle). The compiler or register allocation unit may also ensure that the register file accesses for each instruction are also aligned (each input of a function unit can only come from the bank connected to that input).
A method for aligning input operands stored in a multi-bank register file with function unit inputs, comprising:
A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to align input operands that are stored in a multi-bank register file with function unit inputs, by performing the steps of:
A system for aligning input operands stored in a multi-bank register file with function unit inputs, the system comprising:
Dependencies are inferred from the claim text.