Multi-layer content protecting microcontroller

A secure microcontroller comprising:

• a memory that stores data;
• a processing unit that generates a plurality of commands;
• an access control, coupled to receive the plurality of commands, the access control having a plurality of privilege registers that define access rights to the data stored within the memory;
• a first privilege register, within the plurality of privilege registers, that defines a first set of access rights to a first portion of the data within the memory;
• a second privilege register, within the plurality of privilege registers, that defines a second set of access rights to a second portion of the data within the memory, the second portion being different than the first portion;
• and
• an exception handler, coupled to the access control, that interrupts an access command to the first portion of data in response to the access command failing to meet the first set of access rights associated with the first portion of the data;
• and
• a hardware cipher comprising:
• a hash block, coupled to receive bi-directional data from the memory and the processing unit, the hash block provides fast compression of a long pseudorandom sequence of a cipher key for key generation,
• an address bit shuffler, coupled to a memory management unit and the memory, the address bit shuffler provides scrambled memory locations,
• a cipher block providing ciphering and deciphering and is coupled to the memory management unit and the memory, wherein the hardware cipher receives the cipher key from the memory.