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US 8,555,011 B1Granted
Apparatus and method for a synchronous multi-port memory
AssigneeCypress Semiconductor Corporation
InventorRishi Yadav
Life of this patent
Estimating the term…
Abstract
A method of and apparatus for arbitrating a memory access conflict to a memory array. The apparatus may include selection logic coupled with a plurality of ports and a memory array to arbitrate among a plurality of contending memory access requests and to conditionally block write data from accessing the memory array when write data arrives late in time.
Claims15
A method comprising:
- shifting a memory address of a memory array, a first write-enable value, and a first write data stored in a first input stage to a first delay stage, wherein the first delay stage is configured to store the memory address, first write-enable value, and the first write data;
- shifting the memory address, a second write-enable value, and a second write data stored in a second input stage to a second delay stage, wherein the second delay stage is configured to store the memory address, second write-enable value, and the second write data;
- selecting the memory address from the second input stage and asserting a read enable signal at the memory array;
- and clearing the second write-enable value from a control delay element in the second delay stage to assert a write disable signal at the memory array, the write disable signal conditionally blocking the second write data from accessing the memory array.
1 more element
An apparatus, comprising:
- a plurality of ports;
- and selection logic coupled with the plurality of ports and configured to arbitrate among a plurality of contending memory access requests to a memory array and configured to select a prevailing memory access request from a prevailing one of the plurality of ports, wherein the selection logic is configured to shift a memory address, a write-enable value and a write data from a first input stage to a first delay stage of a memory array, shift the memory address and a read-enable value from a second input stage to a second delay stage of the memory array, select a memory address from a second input stage of a plurality of input stages, assert a read enable signal at a memory array comprising a plurality of memory addresses, and clear a control delay element in a non-prevailing port, wherein the non-prevailing port is configured to assert a disable signal at the memory array in response to the cleared control delay element.
A method, comprising:
- shifting a memory address, a write-enable value and a write data from a first input stage to a first delay stage of a memory array;
- shifting the memory address and a read-enable value from a second input stage to a second delay stage of the memory array;
- selecting the memory address from the second input stage and asserting a read enable signal at the memory array;
- and
- clearing the write-enable value from a control delay element in the first delay stage to assert a write disable signal at the memory array.
2 more elements
Dependencies are inferred from the claim text.