High speed interface for dynamic random access memory (DRAM)
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorLarry J. Thayer
Life of this patent
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Abstract
An interface for a dynamic random access memory (DRAM) includes an interface element coupled to a DRAM chip using a first attachment structure, a first portion of the first attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second portion of the first attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element configured to convert parallel information to serial information and configured to convert serial information to parallel information.
Claims14
An interface for a dynamic random access memory (DRAM), comprising:
- an interface element coupled to a DRAM chip using a first planar attachment structure comprising microbumps, a first plurality of microbumps in the first planar attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second plurality of microbumps in the first planar attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element located over and situated within a periphery of the DRAM chip, the DRAM chip being located over and situated within a periphery of a DRAM package, the interface element configured to convert serial address information to parallel address information, convert serial data to parallel data and convert parallel data to serial data.
A method for forming an interface for a dynamic random access memory (DRAM), comprising:
- coupling an interface element to a DRAM chip using a first planar attachment structure comprising microbumps, a first plurality of microbumps in the first planar attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second plurality of microbumps in the first planar attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element located over and situated within a periphery of the DRAM chip, the DRAM chip being located over and situated within a periphery of a DRAM package;
- and
- converting serial address information to parallel address information, converting parallel data to serial data and converting serial data to parallel data.
An integrated circuit structure, comprising:
- a dynamic random access memory (DRAM) chip coupled to a DRAM package using solder bumps;
- and
- an interface element coupled to the DRAM chip using a planar array of microbumps;
- the interface element configured to provide conversion between a wide bandwidth, low speed, parallel interface associated with the DRAM chip and a narrow bandwidth, high speed, serial interface associated with an input/output (I/O) standard, the planar array of microbumps comprising a first plurality of microbumps to form the wide bandwidth, low speed, parallel interface associated with the DRAM chip, and a second plurality of microbumps, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form the narrow bandwidth, high speed, serial interface associated with an input/output (I/O) standard, the interface element located over and situated within a periphery of the DRAM chip, the DRAM chip being located over and situated within a periphery of a DRAM package.
Dependencies are inferred from the claim text.