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US 8,554,984 B2Granted
Memory system
AssigneeKabushiki Kaisha Toshiba
InventorsJunji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
Life of this patent
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Abstract
A memory system in which speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponds to the logical address, and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position. These forward and reverse lookup tables are linked.
Claims10
A memory system comprising:
- a nonvolatile memory including a plurality of blocks, each one of the plurality of blocks being a data erasing unit and including a plurality of pages, each one of the plurality of pages being a data programming or reading unit;
- and
- a controller configured to:
- receive logical addresses in association with a read request provided by a host apparatus;
- retrieve information associated with physical addresses of the nonvolatile memory by searching a first address management table with the logical addresses;
- readout data from at least one of the plurality of pages indicated by the information associated with the physical addresses of the nonvolatile memory;
- retrieve information associated with the logical addresses by searching a second address management table with the physical addresses of the nonvolatile memory;
- and
- determine a first block including a plurality of invalid data, specify valid data stored in the first block by using the second address management table, and copy valid data stored in the first block to a second block, wherein
- the first address management table is managed with a first management unit smaller than a size of one page and a second management unit larger than a size of one page and smaller than a size of one block,
- the second address management table is managed with the first management unit and the second management unit, and
- the first address management table and the second address management table are linked with each other by information corresponding to the same data.
9 more elements
A memory system comprising:
- a nonvolatile memory including a plurality of blocks, each one of the plurality of blocks being a data erasing unit and including a plurality of pages, each one of the plurality of pages being a data programming or reading unit;
- and
- a controller that performs data transfer between a host apparatus and the nonvolatile memory, wherein
- the controller includes
- a first address management table for managing logical to physical translation information that correlates a logical address specified from the host apparatus with physical addresses of the nonvolatile memory, wherein the first address management table is managed with a first management unit smaller than a size of one page and a second management unit larger than a size of one page and smaller than a size of one block, and
- a second address management table for managing physical to logical translation information that correlates the physical addresses of the nonvolatile memory with the logical address, wherein the second address management table is managed with the first management unit and the second management unit.
3 more elements
A memory system comprising:
- a nonvolatile memory including a plurality of blocks, each one of the plurality of blocks including a plurality of pages;
- and
- a controller configured to
- control the nonvolatile memory;
- manage logical to physical translation information with a first management module smaller than a size of one page and a second management module larger than a size of one page and smaller than a size of one block, the logical to physical translation information correlating a logical address specified from the host apparatus with physical addresses of the nonvolatile memory;
- and
- manage physical to logical translation information with the first management module and the second management module, the physical to logical translation information correlating the physical addresses of the nonvolatile memory with the logical address.
4 more elements
Dependencies are inferred from the claim text.