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US 8,554,972 B2Granted
Logic chip, method and computer program for providing a configuration information for a configurable logic chip
AssigneeFriedrich-Alexander-Universitaet Erlangen-Nuernberg
InventorsDirk Koch, Thilo Streichert, Christian Haubelt, Juergen Teich
Life of this patent
Estimating the term…
Abstract
A logic chip has a plurality of individually-addressable resource blocks, each comprising logic circuitry. The logic chip also has a bus comprising a plurality of bus information lines. A first of the resource blocks has a coupling between a first strict sub-set of the bus information lines and the logic circuitry of the first resource block. A second of the resource blocks, which is adjacent to the first resource block, has a coupling between a second strict sub-set of the bus information lines and the logic circuitry of the second resource blocks. The first and second sub-sets have different bus lines.
Claims16
A logic chip, comprising:
- a plurality of individually-addressable resource blocks, each comprising logic circuitry;
- a bus comprising a plurality of bus information lines;
- wherein a first of the resource blocks comprises a coupling between a first strict sub-set of the bus information lines and the logic circuitry of the first resource block;
- wherein a second of the resource blocks, which is adjacent to the first resource block, comprises a coupling between a second strict sub-set of the bus information lines and the logic circuitry of the second resource blocks;
- wherein the first and second sub-sets comprise different bus lines;
- wherein the bus comprises a plurality of sub-sets of bus information lines;
- wherein the first strict sub-set of the bus information lines is periodically, in terms of space, coupled with resource block logic circuitry once per N of the individually-addressable resource blocks;
- wherein the second strict sub-set of the bus information lines is periodically, in terms of space, coupled with resource block logic circuitry once per N of the individually-addressable resource blocks;
- wherein N is greater than or equal to 2;
- wherein the bus information lines of the first sub-set are coupled to block logic circuitry of different resource blocks than the bus information lines of the second sub-set;
- wherein the different sub-sets of bus information lines are periodically connected to coupling circuits with a periodicity of N resource blocks, such that each of N subsequent resource blocks comprises a coupling circuit connected to a different sub-set of the bus information lines and such that a line of resource blocks comprises a periodic sequence of couplings with different subsets of the bus information lines with a spatial periodicity of N;
- and
- wherein the coupling circuits are configured to provide a coupling between the bus information lines connected thereto and the logic circuitry of the respective resource blocks.
10 more elements
A logic chip, comprising:
- a plurality of individually addressable resource blocks, each comprising logic circuitry;
- a bus comprising a plurality of subsets of bus information lines;
- wherein a first strict subset of the bus information lines is periodically, in terms of space, connected with resource block logic circuitry once per N of the individually addressable resource blocks;
- wherein a second strict subset of the bus information lines is periodically, in terms of space, connected with resource block logic circuitry once per N of the individually addressable resource blocks;
- wherein N is greater than or equal to 2;
- and
- wherein the bus information lines of the first subset are coupled to block logic circuitry of different resource blocks than the bus information lines of the second subset,
- such that a line of resource blocks comprises a periodic sequence of couplings with different subsets of the bus information lines with a spatial periodicity of N.
5 more elements
A method for providing a configuration information for a configurable logic chip, the configurable logic chip comprising a plurality of resource blocks, the method comprising;
- providing a configuration information describing a plurality of individually addressable modules, such that each of the modules comprises one or more resource blocks;
- providing a configuration information describing a bus, such that the bus comprises a plurality of strict subsets of bus information lines,
- wherein the configuration information describing the bus defines that a first strict subset of the bus information lines is periodically, in terms of space, connected to resource block logic circuitry once per N of the resource blocks,
- wherein the configuration information describing the bus defines that a second strict subset of the bus information lines is periodically, in terms of space, connected to resource block logic circuitry once per N of the resource blocks, and
- wherein N is greater than or equal to 2;
- wherein the configuration information describing the bus defines that the bus information lines of the first subset are coupled to block logic circuitry of different resource blocks than the bus information lines of the second subset,
- such that a line of resource blocks comprises a periodic sequence of couplings with different subsets of the bus information lines with a spatial periodicity of N;
- and
- wherein the configuration information describing the plurality of individually addressable modules is provided such that an extension, in terms of resource blocks, of an individually addressable module differs from a bus periodicity of N resource blocks.
6 more elements
A non-transitory digital storage medium comprising a computer program for performing the method for providing a configuration information for a configurable logic chip, the configurable logic chip comprising a plurality of resource blocks, the method comprising;
- providing a configuration information describing a plurality of individually addressable modules, such that each of the modules comprises one or more resource blocks;
- providing a configuration information describing a bus, such that the bus comprises a plurality of strict subsets of bus information lines,
- wherein the configuration information describing the bus defines that a first strict subset of the bus information lines is periodically, in terms of space, connected to resource block logic circuitry once per N of the resource blocks,
- wherein the configuration information describing the bus defines that a second strict subset of the bus information lines is periodically, in terms of space, connected to resource block logic circuitry once per N of the resource blocks, and
- wherein N is greater than or equal to 2;
- wherein the configuration information describing the bus defines that the bus information lines of the first subset are coupled to block logic circuitry of different resource blocks than the bus information lines of the second subset,
- such that a line of resource blocks comprises a periodic sequence of couplings with different subsets of the bus information lines with a spatial periodicity of N;
- and
- wherein the configuration information describing the plurality of individually addressable modules is provided such that an extension, in terms of resource blocks, of an individually addressable module differs from a bus periodicity of N resource blocks.
6 more elements
Dependencies are inferred from the claim text.