Efficient technique for optimal re-use of hardware in the implementation of instructions used in viterbi, turbo and LPDC decoders

An apparatus for computing a MINST function comprising:

• a three input arithmetic logic unit having three inputs and an output, said three input arithmetic logic unit selectively configurable to perform the following combinations of three input operands a, b and threshold (a+b−threshold), (a+b+threshold), (a−b−threshold) and (a−b+threshold) and generate a corresponding Result and Carry at said output, where threshold is a predetermined range constant;
• register set having four registers connected to said output of said three input arithmetic logic unit storing four respective Carry outputs;
• and
• a range selection circuit having four inputs connected to corresponding registers of said register set and two outputs, said range selection circuit operable to
• determine from first and second Carry outputs stored in respective registers of said register set whether a sum of a+b is within a range less than a threshold and greater than an arithmetic inverse of said threshold and generating a corresponding first output, and
• determine from third and fourth Carry outputs stored in respective registers of said register set whether a difference of a−b is within said range less than said threshold and greater than an arithmetic inverse of said threshold and generating a corresponding second output.