System to implement floating point adder using mantissa, rounding, and normalization

A computation processor comprising:

• a computing unit that performs floating point computation of a plurality of input values each of which includes a plurality of bits;
• a shift amount calculating unit that calculates a shift amount of a result of the floating point computation obtained by the computing unit;
• a normalizing unit that includes a plurality of shifting units, and that, by using the shift amount, performs normalization of the result of the floating point computation, by performing a stepwise shift using the shifting units;
• a rounding unit that performs rounding on a result of the normalization by the normalizing unit:
• a predicting unit that, by using the shift amount and in parallel with the normalization, predicts whether each of bits of a first region having a potential of not remaining in a target region of the rounding by being shifted by an amount equal to or more than a predetermined shift amount corresponding to one of the shifting units, and of a second region having a potential of being shifted into the target region of the rounding by being shifted in the normalization performed by the normalizing unit, is included in the target region of the rounding after the normalization, and determines whether all of bits predicted to be included in the target region of the rounding are 1;
• and
• a detecting unit that receives a third region having highest-order bits as many as or less than the predetermined shift amount in the result of the normalization, a forth region having lowest-order bits as many as or less than the predetermined shift amount in the target region of the rounding, and a determination result obtained by the predicting unit to detect a generation of the carry-out by adding 1 to the result of the normalization in the rounding.