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US 8,554,532 B1Granted
Network tearing for circuit simulation
AssigneeWorldwide Pro Ltd.
InventorWilliam Wai Yan Ho
Life of this patent
Estimating the term…
Abstract
A circuit is simulated by using system or network tearing to obtain a real solution. The circuit may be an entire integrated circuit, portion of an integrated circuit, or a circuit block. A circuit simulation technique of the invention generates a system graph, finds a tree, and partitions the tree into two or more subtrees. The technique identifies global links and local links in the graph. Each subtree may be solved individually using distributed, parallel computing. Using the results for the subtrees, the technique obtains a real solution, branch voltages and currents, for the circuit.
Claims20
A method comprising:
- providing a system graph of an electronic circuit;
- identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph;
- partitioning the tree into at least a first subtree and a second subtree;
- forming the first subtree by repeatedly adding branches of the tree to the first subtree when a number of branches in the first subtree is less than a count value;
- forming the second subtree by repeatedly adding branches of the tree to the second subtree, wherein the branches added to the second subtree have not been not assigned to the first subtree;
- identifying a first link of the system graph as a first global link when the first link forms a path from a branch of the first subtree to a branch of the second subtree;
- using at least one processor, calculating a solution to the first subtree independently of the second subtree, while ignoring the first global link;
- and
- using at least one processor, calculating a solution to the second subtree independently of the first subtree, while ignoring the first global link.
6 more elements
A method comprising:
- providing a system graph of an electronic circuit;
- identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph;
- partitioning the tree into at least a first subtree and a second subtree;
- forming the first subtree by repeatedly adding branches of the tree to the first subtree when a number of branches in the first subtree is less than a count value;
- forming the second subtree by repeatedly adding branches of the tree to the second subtree, wherein the branches added to the second subtree have not been not assigned to the first subtree;
- identifying a first link of the system graph as a first global link when the first link forms a path from a branch of the first subtree to a branch of the second subtree;
- using at least one processor, calculating a first solution to the first subtree independently of the second subtree, while ignoring the first global link;
- using at least one processor, calculating a second solution to the second subtree independently of the first subtree, while ignoring the first global link;
- using at least the first and second solutions, calculating a third solution to the system graph of the electronic circuit, wherein the third solution comprises a voltage associated with each node of the electronic circuit;
- identifying independent loops of the circuit;
- summing the voltages for each identified loop and storing the loop sum results;
- summing the currents at each node of the circuit and storing the node sum results;
- summing power consumption of each branch of the circuit and storing the total branch power;
- storing input power to the circuit;
- providing a validation error indication on a computer display when at least one of the identified loops sums to a nonzero value;
- providing a validation error indication on a computer display when at least one of the nodes in the circuit sums to a nonzero value;
- and
- providing a validation error indication on a computer display when the input power is different from the total branch power.
15 more elements
A method comprising:
- providing a system graph of an electronic circuit;
- identifying each branch of the system graph as at least one of a tree branch or a link, wherein the tree branches form a tree of the system graph;
- partitioning the tree into at least a first subtree and a second subtree;
- identifying links of the system graph as at least one of a global link or a local link, wherein a global link forms a path from a branch of the first subtree to a branch of the second subtree;
- using at least one processor, calculating a first solution to the first subtree;
- using at least one processor, calculating a second solution to the second subtree;
- using at least the first and second solutions, calculating a third solution to the system graph of the electronic circuit, wherein the third solution comprises a voltage associated with each node of the electronic circuit;
- identifying independent loops of the circuit;
- summing the voltages for each identified loop and storing the loop sum results;
- summing the currents at each node of the circuit and storing the node sum results;
- summing power consumption of each branch of the circuit and storing the total branch power;
- storing input power to the circuit;
- providing a validation error indication on a computer display when at least one of the identified loops sums to a nonzero value;
- providing a validation error indication on a computer display when at least one of the nodes in the circuit sums to a nonzero value;
- and
- providing a validation error indication on a computer display when the input power is different from the total branch power.
13 more elements
Dependencies are inferred from the claim text.