Methods and systems for property assertion in circuit simulation

#The present invention generally relates to circuit simulation, and more particularly, some embodiments relate to analog circuit simulation and verification.

#Various circuit simulators such as the SPICE simulator are useful tools for solving and verifying electrical circuits. SPICE, which stands for Simulation Program with Integrated Circuit Emphasis, is a general-purpose circuit simulation program for nonlinear dc, nonlinear transient, and linear ac analyses, and is often used to model devices of an integrated circuit design. Circuit descriptions are typically provided to and captured by SPICE in a netlist format, although schematic capture front-ends are also available to allow automated generation of the netlist. The circuits for which the descriptions are captured can be circuits that implement analog, digital, or mixed signal devices.

#The simulator parses the netlist and creates a system of equations for the circuit using methods such as Modified Nodal Analysis (MNA). The equations are solved by various analysis techniques such as DC analysis, AC small-signal analysis, transient analysis, Pole-Zero analysis, and so on. The equations may represent, for example, circuit node voltages, currents, transconductance, and other operating conditions or parameters of the circuit.

#The present invention, in accordance with one or more various embodiments, is described in detail with reference to the following figures. The drawings are provided for purposes of illustration only and merely depict typical or example embodiments of the invention. These drawings are provided to facilitate the reader's understanding of the invention and shall not be considered limiting of the breadth, scope, or applicability of the invention. It should be noted that for clarity and ease of illustration these drawings are not necessarily made to scale.

#FIG. 1 is a diagram illustrating an example tool for circuit design verification in accordance with the systems and methods described herein.

#FIG. 2 is a flowchart illustrating an example method for circuit design simulation and verification in accordance with the systems and methods described herein.

#The figures are not intended to be exhaustive or to limit the invention to the precise form disclosed. It should be understood that the invention can be practiced with modification and alteration, and that the invention be limited only by the claims and the equivalents thereof.

#The present invention relates generally to circuit simulation, and more particularly, some embodiments relate to analog simulation and verification. According to various embodiments of the systems and methods described herein, a set of verification rules for a design are developed, and the circuit design is simulated and verified against those design rules. The state of a circuit at a simulated time, t1, can be evaluated and analyzed to determine if a triggering event has occurred. Upon the occurrence of the triggering event, the state of the circuit at time t1 can be verified against the set of verification rules.

#FIG. 1 is a diagram illustrating an example simulation and verification tool in accordance with the systems and methods described herein. Referring now to FIG. 1, the device includes a simulation module 102 and a verification module 100. The simulation module 102 can be implemented as a circuit simulation tool to simulate circuit designs for verification purposes. In some embodiments, the simulation module can include any suitable circuit simulator such as, for example SPICE simulators or other like circuit simulators. The SPICE simulator, for example, can be implemented to evaluate circuits made up of analog components used to implement analog, digital or mixed signal designs. It should be appreciated that the selection of a suitable circuit simulator is preferably based on the type and characteristics of the components that make up the circuits to be simulated.