US 8,554,514 B2Granted

Test apparatus and test method

AssigneeAdvantest Corporation

InventorsKazuhiro Yamamoto, Toshiyuki Okayasu

Life of this patent

Estimating the term…

Loading patent…

Abstract

A data signal is transmitted synchronously with a clock signal, and contains n phases (n represents an integer of 2 or more) of data for each cycle of the clock signal. A first time to digital converter generates clock change point information which represents the change timing of the clock signal. A second time to digital converter receives a data sequence in increments of cycles of the clock signal, and generates data change point information items which represent the change timing of the data in increments of phases of the data. A calculation unit calculates difference data between the change timing represented by the data change point information and the change point timing represented by the clock change point information in increments of phases. A judgment unit judges a DUT based upon the difference data received from the calculation unit.

Claims14

Dependent claims

A test apparatus configured to receive, from a device under test, a clock signal and a data sequence, which is transmitted synchronously with the clock signal and which contains n (n represents an integer of 2 or more) phases of data for each cycle of the clock signal, and to test the device under test, the test apparatus comprising:

a first time to digital converter configured to receive the clock signal, and to generate clock change point information which represents change timing of the clock signal;
a second time to digital converter configured to receive the data sequence in increments of cycles of the clock signal, and to generate data change point information which represents change timing of the data sequence in increments of phases of the data;
a calculation unit configured to calculate difference data between the change timing represented by the data change point information and the change point timing represented by the clock change point information in increments of phases;
and
a judgment unit configured to evaluate the device under test based upon the difference data received from the calculation unit.

2 more elements

A test method for receiving, from a device under test, a clock signal and a data sequence which is transmitted synchronously with the clock signal and which contains n (n represents an integer of 2 or more) phases for each cycle of the clock signal, and for testing the device under test, the test method comprising:

generating clock change point information which represents a change timing of the clock signal;
generating data change point information which represents a change timing of the data sequence in increments of phases of the data;
calculating difference data between the change timing of the clock signal represented by the clock change point information and the change timing represented by the data change point information in increments of phases;
and
evaluating the device under test based upon the n phases of the difference data.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/997,943Filed 18 Sep 2009
Published: US 2011/0202296 A118 Aug 2011
Granted: 8 Oct 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G01R 31/31726
Timing aspects, e.g. clock distribution, skew, propagation delay: synchronization, e.g. of test, clock or strobe signals; Signals in different…
G01R 31/31727
Testing of digital circuits: clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing…
G01R 31/3193
Tester hardware, i.e. output processing circuits: with comparison between actual response and known fault free response
G01R
Measuring electric variables