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US 8,554,161 B2Granted
Circuit and method for biasing a gallium arsenide (GaAs) power amplifier
AssigneeSkyworks Solutions, Inc.
InventorsZiv Alon, Shiaw W. Chang, Andre Metzger
Life of this patent
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Abstract
A circuit for biasing a gallium arsenide (GaAs) power amplifier includes a reference voltage generator circuit implemented in a gallium arsenide (GaAs) material system, a field effect transistor (FET) bias circuit implemented in the gallium arsenide material system and adapted to receive an output of the reference voltage generator circuit and adapted to provide an output to a radio frequency (RF) amplifier stage.
Claims18
A circuit for biasing a gallium arsenide (GaAs) power amplifier, comprising:
- a reference voltage generator circuit implemented in a gallium arsenide (GaAs) material system and configured to translate an input voltage to thereby provide an output voltage having a greater voltage level than that of the input voltage, the reference voltage regulator circuit further configured to provide temperature and process compensation;
- and
- a field effect transistor (FET) bias circuit implemented in the gallium arsenide material system and adapted to receive an output of the reference voltage generator circuit and adapted to provide an output to a radio frequency (RF) amplifier stage, the reference voltage generator circuit including a first bipolar transistor adapted to compensate for temperature variations in a second bipolar transistor located in the FET bias circuit, a first field effect transistor (FET) adapted to compensate for temperature and process variations in a second FET located in the FET bias circuit, and a third FET adapted to compensate for temperature and process variations in a fourth FET located in the reference voltage generator circuit, the fourth FET having a negative turn on voltage.
A portable transceiver having a circuit for biasing a gallium arsenide (GaAs) power amplifier, comprising:
- a transmitter operatively coupled to a receiver;
- and
- a power amplifier control element including a reference voltage generator circuit implemented in a gallium arsenide (GaAs) material system and configured to translate an input voltage to thereby provide an output voltage having a greater voltage level than that of the input voltage, the reference voltage generator circuit further configured to provide temperature and process compensation, the power amplifier control element further including a field effect transistor (FET) bias circuit implemented in the gallium arsenide material system and adapted to receive an output of the reference voltage generator circuit and adapted to provide an output to a radio frequency (RF) amplifier stage, the reference voltage generator circuit including a first bipolar transistor adapted to compensate for temperature variations in a second bipolar transistor located in the FET bias circuit, a first field effect transistor (FET) adapted to compensate for temperature and process variations in a second FET located in the FET bias circuit, and a third FET adapted to compensate for temperature and process variations in a fourth FET located in the reference voltage generator circuit, the fourth FET having a negative turn on voltage.
A method for biasing a gallium arsenide (GaAs) power amplifier, comprising:
- receiving an analog control signal in a gallium arsenide (GaAs) reference voltage generator circuit configured to provide temperature and process compensation;
- translating the analog control signal to an output voltage having a voltage level greater than that of the analog control signal to generate a bias voltage reference signal compensated for temperature and process variations;
- controlling a current mirror using the bias voltage reference signal to bias a GaAs power amplifier;
- using a first bipolar transistor to compensate for temperature variations in a second bipolar transistor located in a field effect transistor (FET) bias circuit, a first FET to compensate for temperature and process variations in a second FET located in the FET bias circuit, and a third FET to compensate for temperature and process variations in a fourth FET located in the reference voltage generator circuit;
- forming the second bipolar transistor and a third bipolar transistor into a current mirror;
- and
- controlling the current mirror using the second FET in the FET bias circuit.
4 more elements
Dependencies are inferred from the claim text.