ADC-based mixed-mode digital phase-locked loop

A method, comprising:

• receiving a reference signal and a feedback signal at a Phase-to-Digital Converter (PDC);
• using a charge pump within the PDC to drive a node;
• using an Analog-to-Digital Converter (ADC) within the PDC to convert a signal on the node into a first stream of multi-bit digital values;
• using a digital loop filter to filter the first stream of multi-bit digital values and thereby generate a second stream of multi-bit digital values;
• receiving the second stream of multi-bit digital values at a Digitally-Controlled Oscillator (DCO) configured to output a corresponding DCO output signal;
• using a loop divider to frequency divide the DCO output signal and thereby generate the feedback signal, wherein the PDC, the digital loop filer, the DCO and the loop divider are parts of a Phase-Locked Loop (PLL);
• and
• changing a gain of the charge pump such that the charge pump operates with a larger gain when the PLL is in lock, and with a smaller gain when the PLL is not in lock.

A Phase-Locked Loop (PLL) circuit, comprising:

• a digital loop filter configured to receive a stream of multi-bit digital values, to filter the stream, and to thereby generate a stream of digital tuning words;
• an oscillator configured to receive the stream of digital tuning words and to output an oscillating signal;
• a divider configured to receive the oscillating signal and to output a feedback signal;
• means for receiving a reference clock signal and the feedback signal, and for outputting the stream of multi-bit digital values, wherein the means for receiving and for outputting includes a charge pump and an Analog-to-Digital Converter (ADC),
• wherein the charge pump is configured to operate with a larger gain when the PLL is in lock, and to operate with a smaller gain when the PLL is not in lock.

A Phase-Locked Loop (PLL) circuit, comprising:

• a Phase-to-Digital Converter (PDC) configured to receive a reference signal and a feedback signal;
• means within the PDC for driving a node;
• Analog-to-Digital Converter (ADC) means within the PDC for converting a signal on the node into a first stream of multi-bit digital values;
• digital loop filtering means for filtering the first stream of multi-bit digital values and thereby generate a second stream of multi-bit digital values;
• a Digitally-Controlled Oscillator (DCO) configured to receive the second stream of multi-bit digital values and configured to output a corresponding DCO output signal;
• loop dividing means for frequency dividing the corresponding DCO output signal to generate the feedback signal, wherein the PDC, the digital loop filtering means, the DCO, and the loop dividing means are parts of the PLL;
• and
• means for changing a gain of the means within the PDC for driving the node such that the means within the PDC for driving the node operates with a larger gain when the PLL is in lock, and with a smaller gain when the PLL is not in lock.