Phase synchronization apparatus and digital coherent light receiver

A digital coherent light receiver comprising:

• a phase synchronization apparatus including:
• a removal path for removing an error component contained in an input signal and including an averaging section;
• and
• a delay addition path for adding a delay corresponding to a processing time period taken to remove the error component in the removal path, wherein
• the averaging section includes:
• a shift register storing as many data as the maximum number of data to be averaged and successively receiving processing data from which the error component has been extracted in the removal path;
• and
• an obtaining unit for obtaining, among the successive processing data input to the shift register, as many processing data as the number of data to be averaged from a position near the center toward both ends in the shift register.

A method of phase synchronization, comprising:

• taking a processing time period to remove an error component contained in an input signal;
• adding a delay corresponding to the processing time period;
• storing as many data as a maximum number of data to be averaged in a shift register;
• successively receiving processing data from which the error component has been extracted in the shift register;
• obtaining, among the successive processing data input to the shift register, as many processing data as the number of data to be averaged from a position near the center toward both ends in the shift register;
• and
• removing the error component.