Method and apparatus for using DFE in a system with non-continuous data

#This invention relates to memory subsystems that interface with memory devices using decision feedback equalization.

#Typical memory systems use either an asynchronous or synchronous clocking scheme to transmit data between the memory controller and the memory device. Synchronous clocking means that the memory device waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. Synchronous dynamic random access memory (SDRAM) is widely used since such devices typically support higher clock speeds than asynchronous memory devices.

#Double data rate (DDR) SDRAM transfers data on both the rising and falling edges of the clock signal. Such memory devices use a lower clock frequency but require strict control of the timing of the electrical data and clock signals. The first version of such devices (DDR1) achieved nearly twice the bandwidth of a single data rate (SDR) SDRAM running at the same clock frequency. DDR2 and DDR3 SDRAM devices are subsequent improvements over DDR1 devices. Regardless of which type of memory is used, a physical interface (Phy) is coupled directly between the memory controller and the memory devices. The Phy interface generally includes circuitry for handling the timing requirements of the data, command, address and associated strobes. For example, Phy may include delay circuitry configured to properly locate the data strobe in the data eye.

#FIG. 1 is a block diagram of a basic receiver;

#FIG. 2 is a block diagram of a DFE receiver supporting three voltage thresholds;

#FIG. 3 is a block diagram of a threshold generator unit;

#An increase in data rate between a memory device and memory controller and interface circuitry may cause significant problems. An increased data rate typically results in increased distortion in the data channel. As a result, inter-symbol interference (ISI) increases due to an effect where previous data influences the currently transmitted data due to a limit of data channel bandwidth.

#A decision feedback equalizer (DFE) may be used to reduce ISI. In general, a DFE uses previous data to adjust the reference used during data sampling. FIG. 1 is a block diagram of a basic receiver 10 including data sampler 20 and feedback circuit 30. Read data from an attached memory (not shown) is coupled to the Din input 12. Din is an analog signal and is coupled to the non-inverting input of amplifier 22. A voltage reference (Vref) is established at the inverting input of amplifier 22. The output of amplifier 22 (analog) is fed into sense amplifier 24 and the resulting data output 16 (Dout) is a digital representation of the data bit.

#Feedback circuit 30 may be implemented in a variety of configurations. For example, feedback circuit 30 may include a shift register and a resistor network. In operation, as symbols are data output 16 (Dout) from the data sampler 20 is fed back to the shift register which stores a plurality of prior output data bits. These historical data bits may be used to drive the resistor network and adjust the reference voltage at the non inverting input 14. As each subsequent data bit is received, the prior bits are shifted resulting in a weighting function, (e.g., recent bits are weighted more heavily than older bits). In the alternative, feedback circuit 30 may be implemented with two threshold voltages. A first threshold voltage may be selected if the prior data bit was a zero, a second threshold voltage may be selected if the prior data bit was a one. Such circuitry does not address a scenario where prior data history is unavailable.