ADC clock selection based on determined maximum conversion rate

An apparatus for mitigating effects of alias responses in a transceiver comprising:

• the transceiver comprising a temperature compensation unit, a transmitter and a receiver, the receiver comprising an analog-to-digital converter;
• and
• a processing unit, wherein the processing unit is configured to determine a maximum conversion rate for the analog-to-digital converter from among a plurality of possible maximum conversion rates,
• wherein the processing unit is further configured to select a conversion rate for the analog-to-digital converter that is equal to or less than the determined maximum conversion rate based on the determined maximum conversion rate and a frequency of an unwanted signal component of the receiver, and
• wherein the selected conversion rate places an alias response of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component of the receiver.

A computer program product comprising a non-transitory computer-readable medium embodying instructions which, when executed, cause a processing unit to perform a method for mitigating effects of alias responses in a transceiver, the transceiver comprising a temperature compensation unit, a transmitter and a receiver, the receiver comprising an analog-to-digital converter, the method comprising:

• determining a maximum conversion rate of the analog-to-digital converter from among a plurality for possible maximum conversion rates;
• and
• selecting a conversion rate for the analog-to-digital converter that is equal to or less than the determined maximum conversion rate based on the maximum conversion rate and a frequency of an unwanted signal component of the receiver,
• wherein the selected conversion rate places an alias response of the unwanted signal component to a frequency range which is substantially non-overlapping with a wanted signal component of the receiver.