Short and long training fields

An integrated circuit, comprising logic configured to:

• receive a packet comprising a short training field as part of a synchronization header and a long training field as part of the synchronization header;
• use the packet for communication in a wireless network, wherein the packet was generated from:
• a first plurality of symbols comprising real portions and complex portions;
• conjugate symmetry applied to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions;
• the second plurality of symbols transformed using an inverse fast Fourier transform, producing a third plurality of symbols;
• the short training field generated comprising at least one real portion of the third plurality of symbols;
• and
• one or more repetitions of a group of bits in the short training field negated.

A device, comprising:

• a processor;
• a memory coupled to the processor, wherein the processor is configured to;
• receive a first plurality of symbols comprising real portions and complex portions;
• apply conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions;
• transform the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols;
• generate a short training field comprising at least one real portion of the third plurality of symbols;
• negate one or more repetitions of a group of bits in the short training field,
• wherein the processor generates a packet comprising the short training field as part of a synchronization header and a long training field as part of the synchronization header;
• wherein the device uses the packet for communication in a wireless network.

A non-transitory machine-readable storage medium comprising executable instructions that, when executed, cause one or more processors to:

• receive a first plurality of symbols comprising real portions and complex portions;
• apply conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions;
• transform the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols;
• generate a short training field comprising at least one real portion of the third plurality of symbols;
• negate one or more repetitions of a group of bits in the short training field
• wherein the one or more processors are further caused to
• generate a long training field comprising at least one real portion of the third plurality of symbols;
• transmit the short training field and long training field in a wireless network.