Local IO sense accelerator for increasing read/write data transfer speed
AssigneeNanya Technology Corporation
InventorOne-Gyun Na
Life of this patent
Estimating the term…
Abstract
A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.
Claims16
A memory array, comprising:
- at least one differential local bit line pair;
- at least one differential global bit line pair;
- at least a column selection signal line, for charging the differential local bit line pair to a predetermined voltage;
- at least an enable signal line for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value;
- and
- a local sense accelerator, coupled to the differential local bit line pair, for determining the voltage of the differential local bit line pair, and enabling an accelerator signal line for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.
A method for accelerating data transfer in a memory array, comprising:
- providing at least one differential local bit line pair;
- providing at least one differential global bit line pair;
- generating a column selection signal to charge the differential local bit line pair to a predetermined value;
- generating an enable signal to couple the differential local bit line pair to the differential global bit line pair when the voltage of the differential local bit line pair reaches a specific value;
- and
- enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value.
A memory array with a local acceleration block, the array comprising:
- at least one differential local bit line pair;
- at least one differential global bit line pair coupled to the at least one differential local bit line pair;
- and
- at least one enable line coupled to either the local bit line pair or the global bit line pair;
- wherein the local acceleration block is configured to selectively latch one of the differential local bit lines at a high voltage value while causing the other differential local bit line to go to a low voltage value.
Dependencies are inferred from the claim text.