Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
AssigneeRambus Inc.
InventorFrederick A. Ware
Life of this patent
Estimating the term…
Abstract
A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.
Claims20
A memory controller to control a memory device, the memory controller comprising:
- a write circuit operable to transmit at least one of a write-timing reference signal and a write-data signal having a write-signal phase;
- a read circuit operable to receive a read signal having a read-signal phase from the memory device;
- and
- a phase comparator coupled to the write circuit and operable to control the write-signal phase responsive to the read-signal phase.
A memory system comprising:
- a memory device operable to receive at least one of a write-timing reference signal and a write-data signal having a write-signal phase and to convey a read signal of a read-signal phase;
- and
- a memory controller coupled to the memory device and operable to transmit the at least one of the write-timing reference signal and the write-data signal to the memory device and to receive the read signal from the memory device;
- wherein the memory controller adjusts the write-signal phase responsive to the read-signal phase.
A method for synchronizing data transfers between a memory controller and a memory device, the method comprising:
- issuing, from the memory controller to the memory device, a signal of a write phase;
- receiving, at the memory controller from the memory device, a read signal of a read phase;
- and
- adjusting the write phase responsive to the read phase.
A memory system comprising:
- a memory device having means for receiving at least one of a write-timing reference signal and a write-data signal having a write phase and issuing a read signal having a read phase;
- and
- a memory controller having:
- means for issuing the at least one of the write-timing reference signal and the write-data signal to the memory device and receiving the read signal from the memory device;
- and
- means for phase adjusting the at least one of the write-timing reference signal and the write-data signal responsive to phase changes in the read signal.
Dependencies are inferred from the claim text.