Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency
AssigneeRambus Inc.
InventorsJaeha Kim, Brent Haukness
Life of this patent
Estimating the term…
Abstract
A clock-signal generator (e.g. a PLL or a DLL) uses non-volatile memory to store an analog control voltage that determines an output phase and/or frequency of the clock-signal generator. Locked loops take time to lock on a given reference frequency. To keep this time to a minimum, NVM 105 stores the control voltage during periods of inactivity, such as when the signal generator is powered down or in a standby mode. Non-volatile memory stores control voltages during operation in other embodiments to relax the area requirements otherwise required for integration capacitors to store phase and frequency information.
Claims25
A clock-signal generator, comprising:
- a non-volatile analog memory cell to output a stored analog control voltage;
- and
- a clock source to provide a clock signal, the clock source connected to receive the analog control voltage from the non-volatile analog memory cell, wherein the clock signal exhibits a phase, a duty cycle, and a frequency, and at least one of the phase, the duty cycle, and the frequency is controlled by the analog control voltage.
An integrated circuit, comprising:
- a phase detector coupled to receive a first clock signal and a second clock signal, wherein the phase detector outputs phase adjustment signals in response to a phase difference between the first clock signal and the second clock signal;
- programming circuitry coupled to the phase detector to output programming signals responsive to the phase adjustment signals;
- a non-volatile analog memory cell coupled to receive the programming signals from the programming circuitry, wherein the non-volatile memory cell outputs a stored analog control voltage that varies over a range of control voltages in response to the programming signals;
- and
- a clock source from which the second clock signal is derived, the clock source connected to receive the analog control voltage from the non-volatile analog memory cell, wherein the second clock signal exhibits a phase, a duty cycle, and a frequency, and at least one of the phase, the duty cycle, and the frequency is controlled by the analog control voltage.
A method of controlling at least one of phase, frequency, and duty cycle of a clock signal, the method comprising:
- comparing a reference clock signal with a feedback clock signal to generate a clock-adjustment signal;
- and
- programming a non-volatile memory cell to store an analog control signal defined by the clock-adjustment signal, the non-volatile memory cell additionally outputting the analog control signal.
A computer-readable medium having stored thereon a data structure defining a clock generator circuit adapted to produce an output clock signal locked to a reference clock signal, the data structure comprising:
- first data representing a non-volatile analog memory cell to output a stored programmable analog control voltage;
- and
- second data representing a clock source to provide a clock signal, wherein the clock signal exhibits a clock phase, a duty cycle, and a clock frequency, and wherein the analog control signal controls at least one of the clock phase, the duty cycle, and the clock frequency responsive.
A lock-loop circuit, comprising:
- a clock source generating a feedback clock signal having at least one of a feedback-clock phase, a feedback-clock duty cycle, or a feedback-clock frequency that changes in response to an analog control voltage;
- a clock-signal comparator to develop a clock-adjust signal from a reference clock signal and the feedback clock signal;
- and
- means for providing non-volatile analog storage of the analog control voltage, and for changing the stored analog control voltage in response to the clock-adjust signal.
Dependencies are inferred from the claim text.