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US 8,553,472 B2Granted
Memory with a shared I/O including an output data latch having an integrated clamp
AssigneeApple Inc.
InventorsEdward M. McCombs, Daniel C. Chow, Kenneth W. Jones, Alexander E. Runas
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Abstract
A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.
Claims23
A memory comprising:
- a first storage array;
- a second storage array;
- an input/output (I/O) unit coupled to the first storage array and the second storage array, wherein the I/O unit is configured to provide output data from the first storage array and the second storage array via a plurality of data output signal paths;
- wherein the I/O unit includes an output latch configured to force a valid logic level on the plurality of data output signal paths in response to receiving a power down indication.
1 more element
A memory comprising:
- a first storage array;
- a second storage array;
- an input/output (I/O) unit shared between the first and the second storage arrays and configured to provide output data from the first storage array and the second storage array via a plurality of data output signal paths;
- wherein the I/O unit includes an output latch configured to force a valid logic level on the plurality of data output signal paths in response to a first voltage domain that powers a first portion of the output latch being powered down.
1 more element
An integrated circuit comprising:
- a memory;
- an unswitched power rail configured to provide power to an unswitched voltage domain as long as voltage is applied to the integrated circuit;
- and
- a first power gating circuit coupled to the unswitched power rail and configured to provide a first switched voltage domain;
- wherein the memory includes:
- a first storage array;
- a second storage array;
- an input/output (I/O) unit coupled to the first storage array and the second storage array, wherein the I/O unit is configured to provide output data from the first storage array and the second storage array via a plurality of data output signal paths;
- wherein the I/O unit includes an output latch configured to force a valid logic level on the plurality of data output signal paths in response to a first switched voltage domain that powers a first portion of the output latch being powered down.
6 more elements
A mobile communication device comprising:
- a memory;
- and
- a processor coupled to the memory, wherein the processor includes an embedded memory including:
- a first storage array;
- a second storage array;
- a shared input/output (I/O) unit configured to provide output data from the first storage array and the second storage array via a plurality of data output signal paths;
- wherein the I/O unit includes an output latch configured to force a valid logic level on the plurality of data output signal paths in response to an indication that a first switched voltage domain that powers a first portion of the output latch is being powered down.
4 more elements
Dependencies are inferred from the claim text.