Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

A method of accessing and processing data in a memory comprising a plurality of memory devices organized into a plurality of memory ranks, each memory rank comprising a plurality of electrically isolated memory devices, the method comprising:

• receiving at two or more electrically isolated memory devices of one or more memory ranks respective control and address signals;
• processing the respective control and address signals;
• and
• simultaneously accessing the two or more electrically isolated memory devices of one or more memory ranks based on the respective control and address signals.

A method of accessing and processing data in a memory comprising a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a plurality of electrically-isolated memory devices, the method comprising:

• receiving at two or more memory ranks respective control and address signals;
• processing the respective control and address signals;
• and
• simultaneously accessing the two or more memory ranks based on the respective control and address signals.

A method of accessing and processing data in a memory comprising a plurality of memory devices segmented into a plurality of electrically-isolated memory sectors, each memory sector comprising a plurality of memory devices, the method comprising:

• receiving at two or more memory sectors respective control and address signals;
• processing the respective control and address signals;
• and
• simultaneously accessing the two or more memory sectors based on the respective control and address signals.