Memory buffer for buffer-on-board applications
AssigneeDell Products L.P.
InventorStuart Allen Berke
Life of this patent
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Abstract
The present disclosure involves an apparatus. The apparatus includes a decoder that receives an input command signal as its input and generates a first output command signal as its output. The apparatus includes a register component that receives the input command signal as its input and generates a second output command signal as its output. The apparatus further includes a multiplexer that receives a control signal as its control input and receives both the first output command signal and the second output command signal as its data input, the multiplexer being operable to route one of the first and second output command signals to its output in response to the control signal.
Claims16
An apparatus, comprising:
- a memory buffer that is compatible with a Joint Electron Devices Engineering Council (JEDEC) standard, wherein the memory buffer includes:
- a decoder that receives an input command signal as its input and generates a first output command signal as its output;
- a register component that receives the input command signal as its input and generates a second output command signal as its output;
- and
- a multiplexer that receives a control signal as its control input and receives both the first output command signal and the second output command signal as its data input, wherein the control signal configures the multiplexer to operate in one of a JEDEC decode mode in which the multiplexer routes the first output command signal to the output of the multiplexer, and a proprietary decode mode in which the multiplexer routes the second output command signal to the output of the multiplexer.
A method, comprising:
- generating, using a decoder, a first output command signal in response to an input command signal;
- generating, using a register component, a second output command signal in response to the input command signal;
- and
- selecting one of the first output command signal and the second output command signal to be outputted in response to a control signal, wherein the selecting is carried out so that the first output command signal is selected if the control signal indicates that a standard Joint Electron Devices Engineering Council (JEDEC) decode mode is chosen, and the second output command signal is selected if the control signal indicates that a proprietary decode mode is chosen.
A digital apparatus, comprising:
- a decoder component that maps an input command signal to a first output command signal according to a predefined decoding table;
- means for mapping the input command signal to a second output command signal;
- and
- a multiplexer that selects either the first output command signal or the second output command signal to be outputted in response to a control signal, wherein the first output command signal is selected if the control signal indicates that a standard Joint Electron Devices Engineering Council (JEDEC) decode mode is chosen, and the second output command signal is selected if the control signal indicates that a proprietary decode mode is chosen.
Dependencies are inferred from the claim text.