Non-volatile memory device, erasing method thereof, and memory system including the same

A nonvolatile memory device comprising:

• a memory cell array comprising a plurality of memory cell strings which are provided onto a substrate;
• a reading and writing circuit connected to the memory cell strings through a plurality of bit lines, and configured to drive the bit lines;
• an address decoder connected to the memory cell strings through a plurality of word lines, a string selection line and a ground selection line, and configured to drive the word lines and the selection lines;
• and
• a substrate monitor circuit monitoring a voltage level of the substrate wherein the address decoder drives the ground selection line according to a monitored result in an erasing operation.

An erasing method of nonvolatile memory device, the method comprising:

• providing the nonvolatile memory device including a memory string perpendicular to a substrate of a first conductivity, the memory string including a string select transistor, a plurality of memory cells and a ground select transistor using a pillar active body of the first conductivity contacting the substrate;
• applying a word line erase voltage to a plurality of word lines connected to the plurality of memory cells;
• applying a voltage to a ground selection line connected to the ground select transistor;
• applying an erase voltage to the substrate;
• and
• floating the ground selection line in response to a voltage shift of the substrate.

A nonvolatile memory device, comprising:

• a substrate;
• a memory string including a string select transistor, a plurality of memory cells and a ground select transistor using a pillar active body of a first conductivity contacting the substrate;
• an address decoder configured to apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells and apply a voltage to a ground selection line connected to the ground select transistor;
• a substrate bias circuit configured to apply an erase voltage to the substrate;
• and
• a substrate monitor circuit configured to sense a voltage shift of the substrate, wherein the address decoder floats the ground selection line in response to the voltage shift of the substrate.

An erasing method of a nonvolatile memory device including a substrate and a plurality of memory blocks, each including a plurality of memory strings in a two-dimensional array, each including a string selection transistor, a plurality of memory cells, and a ground selection transistor, the plurality of memory strings arranged in rows and columns, wherein columns of the plurality of memory strings are each connected to a corresponding bit line by the corresponding string selection transistor and rows of the plurality of memory strings are each connected to a corresponding string select line by the corresponding string selection transistor, the method comprising;

• selecting one of the plurality of memory blocks for erasing;
• applying a word line erase voltage to a plurality of word lines connected to the plurality of memory cells of the selected memory block;
• applying a voltage to a ground selection line connected to the ground select transistor of the selected memory block and not to at least one unselected memory blocks;
• applying an erase voltage to the substrate;
• and
• floating the ground selection line of the selected memory block in response to a voltage shift of the substrate.

A nonvolatile memory device, comprising:

• a substrate;
• a plurality of memory blocks, each including a plurality of memory strings in a two-dimensional array, each string including a string selection transistor, a plurality of memory cells, and a ground selection transistor, the plurality of memory strings arranged in rows and columns, wherein columns of the plurality of memory strings are each connected to a corresponding bit line by the corresponding string selection transistor and rows of the plurality of memory strings are each connected to a corresponding string select line by the corresponding string selection transistor;
• an address decoder configured to select one of the plurality of memory blocks for erasing, apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells of the selected memory block, apply a voltage to a ground selection line connected to the ground select transistor of the selected memory block and not to the unselected memory blocks;
• a substrate bias circuit configured to apply an erase voltage to the substrate;
• and
• a substrate monitor circuit configured to sense a voltage shift of the substrate, wherein the address decoder float the ground selection line in response to the voltage shift of the substrate.

A nonvolatile memory device comprising:

• a memory cell array comprising a plurality of memory cell strings which are provided onto a substrate;
• a reading and writing circuit connected to the memory cell strings through a plurality of bit lines, and configured to drive the bit lines;
• and
• an address decoder connected to the memory cell strings through a plurality of word lines, a string selection line and a ground selection line, and configured to drive the word lines and the selection lines;
• wherein the address decoder drives the ground selection line in an erasing operation by waiting a delay time after applying a voltage to the substrate.

A nonvolatile memory device, comprising:

• a substrate;
• a memory string including a string select transistor, a plurality of memory cells and a ground select transistor using a pillar active body of a first conductivity contacting the substrate;
• an address decoder configured to apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells and apply a voltage to a ground selection line connected to the ground select transistor;
• a substrate bias circuit configured to apply an erase voltage to the substrate;
• and
• wherein the address decoder waits a delay time and then floats the ground selection line in response to the voltage shift of the substrate.

A nonvolatile memory device, comprising:

• a substrate;
• a plurality of memory blocks, each including a plurality of memory strings in a two-dimensional array, each string including a string selection transistor, a plurality of memory cells, and a ground selection transistor, the plurality of memory strings arranged in rows and columns, wherein columns of the plurality of memory strings are each connected to a corresponding bit line by the corresponding string selection transistor and rows of the plurality of memory strings are each connected to a corresponding string select line by the corresponding string selection transistor;
• an address decoder configured to select one of the plurality of memory blocks for erasing, apply a word line erase voltage to a plurality of word lines connected to the plurality of memory cells of the selected memory block, apply a voltage to a ground selection line connected to the ground select transistor of the selected memory block and not to the unselected memory blocks;
• and
• a substrate bias circuit configured to apply an erase voltage to the substrate;
• wherein the address decoder waits a delay time and then floats the ground selection line in response to the voltage shift of the substrate.