Nonvolatile programmable logic switch

A nonvolatile programmable logic switch, comprising:

• an isolation region provided on a semiconductor substrate;
• a first semiconductor region with a first conductive type and a second semiconductor region with a second conductive type provided on the semiconductor substrate, the first semiconductor region and the second semiconductor region being separated each other by the isolation region;
• a first diffusion region, a second diffusion region and a third diffusion region provided separately from each other on the first semiconductor region, the first diffusion region, the second diffusion region and the third diffusion region having the second conductive type;
• a first memory cell transistor comprising,
• a first insulator provided on a first portion of the first semiconductor region between the first diffusion region and the second diffusion region,
• a first charge accumulation film accumulating electric charges provided on the first insulator,
• a second insulator provided on the first charge accumulation film, and
• a first control gate provided on the second insulator;
• a second memory cell transistor comprising,
• a third insulator provided on a second portion of the first semiconductor region between the second diffusion region and the third diffusion region,
• a second charge accumulation film accumulating electric charges provided on the third insulator,
• a fourth insulator provided on the second charge accumulation film, and
• a second control gate provided on the fourth insulator;
• a pass transistor comprising,
• a fourth diffusion region and a fifth diffusion region separately provided each other in the second semiconductor region, both the fourth diffusion region and the fifth diffusion region having the second conductive type,
• a fifth insulator provided on a third portion of the second semiconductor region between the fourth diffusion region and the fifth diffusion region,
• a gate electrode provided on the fifth insulator and connected to the second diffusion region;
• and
• a first substrate electrode provided on the semiconductor substrate applying a first substrate voltage to the second semiconductor region;
• wherein
• a writing voltage is applied to the first control gate and the second control gate, a first voltage is applied to one of the first diffusion region and the third diffusion region and a second voltage which is lower than the first voltage is applied to the other of the first diffusion region and the third diffusion region, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to the first substrate electrode, when data is written into the first memory cell transistor or the second memory cell transistor.