Method of programming a multi-level memory device

A method comprising:

• applying a series of one or more programming pulses to a multi-level memory cell to set a threshold voltage of the multi-level memory cell at a level above a program voltage;
• and
• applying a test read voltage to the multi-level memory cell to verify that the multi-level memory cell is set at the level, the test read voltage being less than the program voltage and greater than a read voltage to be used to read a state of the multi-level memory cell;
• programming a least significant bit (LSB) of a logic value to be associated with the multi-level memory cell by said applying of the series of one or more programming pulses;
• programming a most significant bit (MSB) of the logic value by applying another series of one or more programming pulses to the multi-level memory cell to set the threshold voltage at another level above another program voltage;
• and
• applying another test read voltage to the multi-level memory cell to verify that the multi-level cell is set at the another level, the another read voltage being smaller than the another program voltage, wherein said programming the most significant bit further comprises:
• loading the MSB into a first (MSB) latch of a page buffer;
• retrieving the LSB from the multi-level cell with the read voltage;
• loading the LSB into a second latch and a third latch of the page buffer;
• and
• applying the another series of one or more programming pulses based at least in part on the MSB and the LSB loaded into the first latch and the second latch, respectively.

A method comprising:

• applying a series of one or more programming pulses to a multi-level memory cell to set a threshold voltage of the multi-level memory cell at a level above a program voltage;
• applying the program voltage to a control gate of the multi-level memory cell to verify that the multi-level memory cell is set at the level;
• after verifying that the multi-level memory cell is set at the level using the program voltage, further applying a test read voltage to the control gate of the multi-level memory cell to again verity that the multi-level memory cell is set at the level, the test read voltage being less than the program voltage and greater than a read voltage to be used to read a state of the multi-level memory cell associated with the level;
• applying another series of one or more programming pulses to the multi-level memory cell to set a threshold voltage of the multi-level memory cell at a second level above a second program voltage;
• applying the second program voltage to the control gate of the multi-level memory cell to verify that the multi-level memory cell is set to the second level;
• and
• after verifying that the multi-level memory cell is set at the second level using the second program voltage, further applying, before any further pulses, the second test read voltage to the control gate of the multi-level memory cell to again verify that the multi-level memory cell is set at the second level, the second test read voltage being less than the second program voltage and greater than a read voltage to be used to read a state of the multi-level memory cell associated with the second level.

A method comprising:

• if a first bit of a logic value to be associated with a multi-level memory cell has a first value:
• applying a series of one or more programming pulses to the multi-level memory cell to set a threshold voltage of the multi-level memory cell at a level above a program voltage;
• applying the program voltage to a control gate of the multi-level memory cell to verify that the multi-level memory cell has a threshold voltage above the program voltage;
• and
• after verifying that the multi-level memory cell is set at the level using the program voltage, further applying, before any further pulses, a test read voltage to the control gate of the multi-level memory cell to again verify that the multi-level memory cell is set at the level, the test read voltage being less than the program voltage and greater than a read voltage to be used to read a state of the multi-level memory cell associated with the level;
• if a second bit of the logic value to be associated with the multi-level memory cell has the first value:
• applying another series of one or more programming pulses to the multi-level memory cell to set the threshold voltage of the multi-level memory cell at a second level above a second program voltage;
• applying the second program voltage to the control gate of the multi-level memory cell to verify that the multi-level memory cell is set to the second level;
• and
• after verifying that the multi-level memory cell is set at the second level using the second program voltage, further applying, before any further pulses, a second test read voltage to the control gate of the multi-level memory cell to again verify that the multi-level memory cell is set at the second level, the second test read voltage being less than the second program voltage and greater than a read voltage to be used to read a state of the multi-level memory cell associated with the second level;
• wherein the second program voltage has a first voltage value if the first bit of the logic value has the first value;
• and
• wherein the second program voltage has a second voltage value different from the first voltage value if the first bit of the logic value has a second value different from the first value.