SRAM cells, memory circuits, systems, and fabrication methods thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen Hung Lee, Hung-Jen Liao
Life of this patent
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Abstract
A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line.
Claims20
A static random access memory (SRAM) cell comprising:
- a pair of cross-coupled inverters having a first node and a second node;
- a first transistor coupled between the first node and a first bit line;
- a second transistor coupled between the second node and a second bit line;
- a third transistor having a gate coupled with the first node;
- and
- a fourth transistor coupled between the third transistor and a third bit line,
- the third transistor having a threshold voltage that is higher than that of the fourth transistor by about 10% or more.
A static random access memory (SRAM) circuit comprising:
- a sense amplifier;
- and
- a SRAM cell coupled with the sense amplifier, the SRAM cell comprising:
- a pair of cross-coupled inverters having a first node and a second node;
- a first transistor coupled between the first node and a first bit line;
- a second transistor coupled between the second node and a second bit line;
- a third transistor having a gate coupled with the first node;
- a fourth transistor coupled between the third transistor and a third bit line,
- the third transistor having a threshold voltage that is higher than that of the fourth transistor by about 10% or more.
A memory cell comprising:
- a pair of cross-coupled inverters, comprising:
- a first transistor of a first type, a source of the first transistor coupled to a first power node;
- and
- a second transistor of a second type, a source of the second transistor coupled to a second power node, a drain of the second transistor coupled to a drain of the first transistor, and a gate of the second transistor coupled to a gate of the first transistor;
- a third transistor of the second type, a source of the third transistor coupled to the second power node, and a gate of the third transistor coupled to the drain of the second transistor;
- and
- a fourth transistor of the second type, a source of the fourth transistor coupled to a drain of the third transistor, and a drain of the fourth transistor coupled to a bit line,
- the third transistor having a threshold voltage that is higher than that of the fourth transistor by about 10% or more.
Dependencies are inferred from the claim text.