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US 8,553,441 B1Granted
Ternary content addressable memory cell having two transistor pull-down stack
AssigneeNetLogic Microsystems, Inc.
InventorDimitri Argyres
Life of this patent
Estimating the term…
Abstract
Ternary CAM cells include a compare circuit including a discharge path having only two pull-down transistors coupled between the match line and ground potential.
Claims17
A ternary content addressable memory (CAM) cell for storing a data value having one of three possible states represented by a data bit and a mask bit, the CAM cell comprising:
- a data cell to store the data bit;
- a mask cell to store the mask bit;
- and
- a compare circuit coupled to the data cell, the mask cell, and a match line, the compare circuit configured to discharge the match line through one of two paths between the match line and ground potential if there is a mismatch condition between a comparand bit and the data value, wherein each of the two paths consists essentially of only two transistors connected in series between the match line and ground potential, and wherein a first of the two transistors has a gate to receive a bit corresponding to the mask bit, and a second of the two transistors has a gate to be selectively driven by a bit corresponding to the data bit.
1 more element
A ternary content addressable memory (CAM) cell for storing a data value having one of three possible states represented by a data bit and a mask bit, the CAM cell comprising:
- a data cell to store the data bit;
- a mask cell to store the mask bit;
- and
- a compare circuit coupled to the data cell and the mask cell, the compare circuit comprising:
- first and second match line pull-down transistors connected in parallel between a match line and a discharge node, wherein the first match line pull-down transistor has a gate to be selectively driven by the data bit in response to a comparand bit, and the second match line pull-down transistor has a gate to be selectively driven by a complemented data bit in response to a complemented comparand bit;
- and
- a mask discharge transistor connected between the discharge node and ground potential, and having a gate to receive a bit corresponding to the mask bit.
4 more elements
Dependencies are inferred from the claim text.