Back to results
US 8,553,165 B2Granted
Liquid crystal display panel, pixel array substrate and pixel structure thereof for solving greenish problem
AssigneeAu Optronics Corporation
InventorsPeng-Bo Xi, Yi-Jen Chen, Shin-Hung Yeh, Ya-Ling Hsu, Wei-Kai Huang
Life of this patent
Estimating the term…
Abstract
A pixel structure includes a plurality of data lines and a common line. The common line overlaps each data line, and is coupled with each data line to respectively form a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, a fourth coupling capacitor, a fifth coupling capacitor, and a sixth coupling capacitor. The third coupling capacitor is smaller than the second coupling capacitor, and the fifth coupling capacitor is smaller than the fourth coupling capacitor.
Claims38
A pixel structure, disposed on a substrate, the substrate comprising a first sub-pixel region, a second sub-pixel region and a third sub-pixel region, and the pixel structure comprising:
- a plurality of data lines, comprising:
- a first data line, disposed at a side of the first sub-pixel region;
- a second data line and a third data line, disposed between the first sub-pixel region and the second sub-pixel region;
- a fourth data line and a fifth data line, disposed between the second sub-pixel region and the third sub-pixel region;
- and
- a sixth data line, disposed at a side of the third sub-pixel region;
- a scan line, crossing the data lines, and the scan line passing through the first sub-pixel region, the second sub-pixel region and the third sub-pixel region;
- a first upper sub-pixel, a second upper sub-pixel and a third upper sub-pixel, disposed at an upper side of the scan line in the first sub-pixel region, the second sub-pixel region and the third sub-pixel region respectively, and the first upper sub-pixel, the second upper sub-pixel and the third upper sub-pixel being electrically connected to the scan line, wherein the first upper sub-pixel is electrically connected to the first data line, the second upper sub-pixel is electrically connected to the fourth data line, and the third upper sub-pixel is electrically connected to the fifth data line;
- a first lower sub-pixel, a second lower sub-pixel and a third lower sub-pixel, disposed at a lower side of the scan line in the first sub-pixel region, the second sub-pixel region and the third sub-pixel region respectively, and the first lower sub-pixel, the second lower sub-pixel and the third lower sub-pixel being electrically connected to the scan line, wherein the first lower sub-pixel is electrically connected to the second data line, the second lower sub-pixel is electrically connected to the third data line, and the third lower sub-pixel is electrically connected to the sixth data line;
- a first common line, passing through the first upper sub-pixel, the second upper sub-pixel and the third upper sub-pixel, and partially overlapping the data lines,
- wherein a first upper coupling capacitor is formed between the first common line and the first data line, a second upper coupling capacitor is formed between the first common line and the second data line, a third upper coupling capacitor is formed between the first common line and the third data line, a fourth upper coupling capacitor is formed between the first common line and the fourth data line, a fifth upper coupling capacitor is formed between the first common line and the fifth data line, and a sixth upper coupling capacitor is formed between the first common line and the sixth data line, and
- wherein the third upper coupling capacitor is smaller than the second upper coupling capacitor, and the fifth upper coupling capacitor is smaller than the fourth upper coupling capacitor;
- and
- a second common line, passing through the first lower sub-pixel, the second lower sub-pixel and the third lower sub-pixel, and partially overlapping the data lines.
11 more elements
A pixel array substrate, comprising:
- a substrate, comprising a plurality of first pixel regions and a plurality of second pixel regions, the first pixel regions and the second pixel regions being arranged as a matrix, wherein in the same row or in the same column, each first pixel region and each second pixel region are arranged alternatively in sequence, and each of each first pixel region and each second pixel region respectively has a first sub-pixel region, a second sub-pixel region and a third sub-pixel region defined therein;
- and
- a plurality of first pixel structures and a plurality of second pixel structures, disposed on the substrate, each first pixel structure being disposed respectively in each first pixel region, each second pixel structure being disposed respectively in each second pixel region, each of each first pixel structure and each second pixel structure respectively comprising:
- a plurality of data lines, comprising:
- a first data line, disposed at a side of the first sub-pixel region;
- a second data line and a third data line, disposed between the first sub-pixel region and the second sub-pixel region;
- a fourth data line and a fifth data line, disposed between the second sub-pixel region and the third sub-pixel region;
- and
- a sixth data line, disposed at a side of the third sub-pixel region;
- a scan line, crossing the data lines, and the scan line passing through the first sub-pixel region, the second sub-pixel region and the third sub-pixel region;
- a first upper sub-pixel, a second upper sub-pixel and a third upper sub-pixel, disposed at an upper side of the scan line in the first sub-pixel region, the second sub-pixel region and the third sub-pixel region respectively, and the first upper sub-pixel, the second upper sub-pixel and the third upper sub-pixel being electrically connected to the scan line, wherein in each first pixel structure, the first upper sub-pixel is electrically connected to the first data line, the second upper sub-pixel is electrically connected to the fourth data line, and the third upper sub-pixel is electrically connected to the fifth data line, and wherein in each second pixel structure, the first upper sub-pixel is electrically connected to the second data line, the second upper sub-pixel is electrically connected to the third data line, and the third upper sub-pixel is electrically connected to the sixth data line;
- a first lower sub-pixel, a second lower sub-pixel and a third lower sub-pixel, disposed at a lower side of the scan line in the first sub-pixel region, the second sub-pixel region and the third sub-pixel region respectively, and the first lower sub-pixel, the second lower sub-pixel and the third lower sub-pixel being electrically connected to the scan line, wherein in each first pixel structure, the first lower sub-pixel is electrically connected to the second data line, the second lower sub-pixel is electrically connected to the third data line, and the third lower sub-pixel is electrically connected to the sixth data line, and wherein in each second pixel structure, the first lower sub-pixel is electrically connected to the first data line, the second lower sub-pixel is electrically connected to the fourth data line, and the third lower sub-pixel is electrically connected to the fifth data line;
- a first common line, passing through the first upper sub-pixel, the second upper sub-pixel and the third upper sub-pixel, and partially overlapping the data lines, wherein a first upper coupling capacitor is formed between the first common line and the first data line, a second upper coupling capacitor is formed between the first common line and the second data line, a third upper coupling capacitor is formed between the first common line and the third data line, a fourth upper coupling capacitor is formed between the first common line and the fourth data line, a fifth upper coupling capacitor is formed between the first common line and the fifth data line, and a sixth upper coupling capacitor is formed between the first common line and the sixth data line, and wherein in each first pixel structure, the third upper coupling capacitor is smaller than the second upper coupling capacitor, and the fifth upper coupling capacitor is smaller than the fourth upper coupling capacitor;
- and
- a second common line, passing through the first lower sub-pixel, the second lower sub-pixel and the third lower sub-pixel, and partially overlapping the data lines.
12 more elements
A liquid crystal display panel, comprising:
- a first substrate, comprising a plurality of first pixel regions and a plurality of second pixel regions, the first pixel regions and the second pixel regions being arranged as a matrix, wherein in the same row or in the same column, each first pixel region and each second pixel region are arranged alternatively in sequence, and each of each first pixel region and each second pixel region respectively has a first sub-pixel region, a second sub-pixel region and a third sub-pixel region defined therein;
- a plurality of first pixel structures and a plurality of second pixel structures, disposed on the first substrate, each first pixel structure being disposed respectively in each first pixel region, each second pixel structure being disposed respectively in each second pixel region, each of each first pixel structure and each second pixel structure respectively comprising:
- a plurality of data lines, comprising:
- a first data line, disposed at a side of the first sub-pixel region;
- a second data line and a third data line, disposed between the first sub-pixel region and the second sub-pixel region;
- a fourth data line and a fifth data line, disposed between the second sub-pixel region and the third sub-pixel region;
- and
- a sixth data line, disposed at a side of the third sub-pixel region;
- a scan line, crossing the data lines, and the scan line passing through the first sub-pixel region, the second sub-pixel region and the third sub-pixel region;
- a first upper sub-pixel, a second upper sub-pixel and a third upper sub-pixel, disposed at an upper side of the scan line in the first sub-pixel region, the second sub-pixel region and the third sub-pixel region respectively, and the first upper sub-pixel, the second upper sub-pixel and the third upper sub-pixel being electrically connected to the scan line, wherein in each first pixel structure, the first upper sub-pixel is electrically connected to the first data line, the second upper sub-pixel is electrically connected to the fourth data line, and the third upper sub-pixel is electrically connected to the fifth data line, and wherein in each second pixel structure, the first upper sub-pixel is electrically connected to the second data line, the second upper sub-pixel is electrically connected to the third data line, and the third upper sub-pixel is electrically connected to the sixth data line;
- a first lower sub-pixel, a second lower sub-pixel and a third lower sub-pixel, disposed at a lower side of the scan line in the first sub-pixel region, the second sub-pixel region and the third sub-pixel region respectively, and the first lower sub-pixel, the second lower sub-pixel and the third lower sub-pixel being electrically connected to the scan line, wherein in each first pixel structures, the first lower sub-pixel is electrically connected to the second data line, the second lower sub-pixel is electrically connected to the third data line, and the third lower sub-pixel is electrically connected to the sixth data line, and wherein in each second pixel structure, the first lower sub-pixel is electrically connected to the first data line, the second lower sub-pixel is electrically connected to the fourth data line, and the third lower sub-pixel is electrically connected to the fifth data line;
- a first common line, passing through the first upper sub-pixel, the second upper sub-pixel and the third upper sub-pixel, and partially overlapping the data lines, wherein a first upper coupling capacitor is formed between the first common line and the first data line, a second upper coupling capacitor is formed between the first common line and the second data line, a third upper coupling capacitor is formed between the first common line and the third data line, a fourth upper coupling capacitor is formed between the first common line and the fourth data line, a fifth upper coupling capacitor is formed between the first common line and the fifth data line, and a sixth upper coupling capacitor is formed between the first common line and the sixth data line, and in each first pixel structure, the third upper coupling capacitor is smaller than the second upper coupling capacitor, and the fifth upper coupling capacitor is smaller than the fourth upper coupling capacitor;
- and
- a second common line, passing through the first lower sub-pixel, the second lower sub-pixel and the third lower sub-pixel, and partially overlapping the data lines;
- a second substrate, disposed opposite to the first substrate;
- and
- a liquid crystal layer, disposed between the first substrate and the second substrate.
14 more elements
Dependencies are inferred from the claim text.