A/D converter and readout circuit
AssigneeNational University Corporation Shizuoka University
InventorShoji Kawahito
Life of this patent
Estimating the term…
Loading patent…
AssigneeNational University Corporation Shizuoka University
InventorShoji Kawahito
Estimating the term…
An A/D converter 11 performs multiple-times sampling on a first signal S1 in a first period T1 while performing multiple-times sampling on a second signal S2 in a second period T2. An A/D converter circuit 17 provides a digital signal in response to a signal from an output 15b of a gain stage 15 in the second period T2. The digital signal may have a value “1” or a value “0”. The A/D converter circuit 17 includes a circuit 18 providing a signal SA/DM corresponding to the number of times the value “1” appears. A switch 24 operates in response to a clock signal φs and is used to sample a signal from a pixel 2a. In a first capacitor circuit 27, a switch 29 and a capacitor 31 are connected to an inverting input 23a and a non-inverting output 23b, respectively. The switch 29 operates in response to a clock signal φ3 and is used for integration in the capacitor 31.
An A/D converter for an image sensor, comprising:
Dependencies are inferred from the claim text.