Shift register circuit

A shift register circuit for providing plural gate signals to plural gate lines, the shift register circuit comprising a plurality of shift register stages, an Nth shift register stage of the shift register stages comprising:

• a driving unit, electrically connected to an Nth gate line of the gate lines, for outputting an Nth gate signal of the gate signals according to a first system clock and an Nth driving control voltage, wherein the Nth gate line is employed to transmit the Nth gate signal;
• an input unit, electrically connected to the driving unit, for outputting the Nth driving control voltage according to an input control signal and a first input signal;
• a driving adjustment unit, electrically connected to the driving unit and the input unit, for adjusting the Nth driving control voltage according to a second input signal and a third input signal, the driving adjustment unit comprising:
• a first transistor having a first end for receiving the second input signal, a second end for outputting an adjustment control voltage, and a gate end for receiving the third input signal;
• a first capacitor having a first end electrically connected to the second end of the first transistor, and a second end electrically connected to the input unit and the driving unit;
• and
• a second capacitor having a first end directly connected to the second end of the first transistor, and a second end for receiving a fifth input signal;
• and
• a first pull-down unit, directly connected to the input unit and the Nth gate line, for pulling down the Nth gate signal and the Nth driving control voltage according to a fourth input signal.