System and method of clocking low sample rate analog to digital converters while minimizing linearity errors
AssigneeTexas Instruments Incorporated
InventorsHaydar Bilhan, Maher Mahmoud Sarraj
Life of this patent
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Abstract
A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.
Claims13
A successive approximation register analog to digital converter comprising:
- (a) a switched capacitor digital to analog converter having an output;
- (b) a comparator having an input sense node coupled to the output of the switched capacitor digital to analog converter;
- (c) at least one reset switch coupled between the input sense node on the comparator and a reference voltage;
- and,
- (d) a clocking system to provide timing to operate at lower sample rates wherein successive approximation cycles are clocked at the same clock pulse irrespective of the sample rate but wherein an end of conversion signal is delayed to mimic a slower sample rate.
An analog to digital converter comprising:
- (a) a switched capacitor digital to analog converter having an output;
- (b) a comparator having an input sense node;
- (c) at least one reset switch coupled between the input sense node on the comparator and a reference voltage;
- and
- (d) a clocking system having an end of conversion generator and a timing generator both having a first input coupled to a start of conversion signal, the end of conversion generator having a second input coupled to a system clock and an output, a clock multiplier having an input coupled to the system clock and an output coupled to a second input on the timing generator.
A method of successive approximation conversion in an analog to digital converter having a comparator, at least one reset switch coupled to an input sense node on the comparator and a switched capacitor DAC, comprising steps of:
- (a) coupling the input sense node of the comparator to a reference voltage during periods of non-conversion;
- (b) using a constant clock frequency for switching the switched capacitor DAC and at the least one reset switch;
- and,
- (c) delaying issuance of an end of conversion signal to mimic a slower sample rate.
Dependencies are inferred from the claim text.