Output impedance compensation for voltage regulators

An impedance compensation circuit (ICC) for being configured at an output terminal (OT) of a DC voltage regulator circuit (RC), said ICC comprising:

• individual components, further comprising:
• a serial combination of an inductance (L1) and a resistance (R1), to form a first element;
• a parallel combination of a resistance (R2) and said first element to form a two terminal second element, said second element being connectable to said OT by a first terminal;
• and
• a serial combination of a capacitance (C3) and a resistance (R3), to form a third element that is connected between a second terminal of said second element and a common terminal, wherein an output (Vout) from said ICC can be provided between said second terminal and said common terminal for sourcing a load R4, wherein
• said L1 includes any inductance in connecting traces or wires between said OT and said C3, said L1 and an output inductance (Lout) of said RC combinedly forming an inductive element of a source impedance, said source impedance being a series combination of an inherent output impedance characteristic of said RC and a first impedance due to said second element, wherein
• said R1 includes a resistance of L1 and any resistance in connecting traces or wires between said OT and said C3, said R1 and an output resistance (Rout) of said RC combinedly forming a resistive element of said source impedance, said R1 coordinating with said R3 to establish said source impedance, wherein
• said R2 operatively sets an upper limit to an impedance rise of said L1 at high frequencies normally above a first defined frequency range (DFR) and said C3 forms a capacitive element of a load impedance, wherein said load impedance is a parallel combination of a second impedance due to said third element and said load R4, when said ICC is configured with said RC and said load R4, wherein
• said R3 is a serial combination of:
• a) an equivalent resistance of said C3, b) any resistance in connecting traces or wires between said C3 and said common terminal, and c) any added resistance necessary to achieve a desired value of said R3, wherein said R3 is substantially equal to (said R1+said Rout) and defines a resistive element of said load impedance, wherein
• said individual components are workable in combination with said inherent output impedance characteristic of said RC, wherein
• said individual components are optimized for providing a substantially uniform AC output impedance characteristic and impedance phase over said first DFR and an operating idle current under said load R4, by creating a condition where said source impedance and said load impedance are complex conjugates.

A method of compensating a DC voltage regulator circuit (RC), said method comprises:

• configuring an impedance compensation circuit (ICC) at an output terminal (OT) of said RC, wherein said ICC comprises individual components that are workable in combination with an inherent output impedance characteristic of said RC, said individual components being optimizable for providing a substantially uniform AC output impedance characteristic and impedance phase over a first defined frequency range (DFR) and an operating idle current under a load, by creating a condition where a source impedance and a load impedance are complex conjugates, said source impedance being a series combination of said inherent output impedance characteristic of said RC and a first impedance due to a first portion of said individual components, while said load impedance is a parallel combination of a second impedance due to a second portion of said individual components and said load, when said ICC is configured with said RC and said load;
• establishing said first DFR;
• measuring said operating idle current;
• measuring said inherent output impedance characteristic of said RC;
• calculating an inductance of said RC within said first DFR;
• and
• optimizing said individual components for providing said substantially uniform AC output impedance characteristic and impedance phase over said first DFR and said operating idle current, by creating said condition where said source impedance and said load impedance are complex conjugates.