Substrate bias control circuit for system on chip

A substrate bias control circuit, comprising:

• a process voltage temperature (PVT) effect transducer for responding to a PVT effect;
• a PVT effect quantifier coupled to the PVT effect transducer for quantifying the PVT effect to provide an output, the PVT effect quantifier including
• at least one counter, and
• a period generator for providing a time period for the at least one counter;
• and
• a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an n-channel metal-oxide semiconductor (NMOS) transistor,
• wherein the bias controller configured to compare the output received from the PVT effect quantifier to a first threshold value, and decrease the bias voltage if the output is higher than the first threshold value.

An integrated circuit, comprising:

• a PMOS transistor;
• an NMOS transistor;
• a substrate bias control circuit for providing a first bias voltage for the PMOS transistor and a second bias voltage for the NMOS transistor, the substrate bias control circuit comprising:
• a process voltage temperature (PVT) effect transducer for responding to a PVT effect;
• a PVT effect quantifier coupled to the PVT effect transducer for quantifying the PVT effect to provide an output, the PVT effect quantifier including
• at least one counter, and
• a period generator for providing a time period for the at least one counter;
• and
• a bias controller configured to receive the output of the PVT effect quantifier and provide the first bias voltage and the second bias voltage, the bias controller including a first bias voltage comparator and a second bias voltage comparator,
• wherein the PVT effect transducer comprises
• a first ring oscillator connected to a first counter of the at least one counter that provides a first counter value of the first ring oscillator during the time period, and
• a second ring oscillator connected to a second counter of the at least one counter that provides a second counter value of the second ring oscillator during the time period, and
• wherein the PVT effect quantifier further comprises a counter comparator for comparing the first counter value and the second counter value and for selecting the first counter value or the second counter value as the output of the PVT effect quantifier.

An integrated circuit, comprising:

• a PMOS transistor;
• an NMOS transistor;
• a substrate bias control circuit for providing a first bias voltage for the PMOS transistor and a second bias voltage for the NMOS transistor, the substrate bias control circuit including:
• a process voltage temperature (PVT) effect transducer for responding to a PVT effect, wherein the PVT effect transducer comprises a first ring oscillator;
• a PVT effect quantifier coupled to the PVT effect transducer for quantifying the PVT effect to provide an output, the PVT effect quantifier including
• at least one counter,
• a period generator for providing a time period for the at least one counter, and
• a comparator, wherein the first ring oscillator is connected to a first counter of the at least one counter that provides a first counter value of the
• first ring oscillator during the time period;
• and
• a bias controller configured to receive the output from the PVT effect quantifier and provide the first bias voltage and the second bias voltage, the bias controller including a first bias voltage comparator and a second bias voltage comparator, wherein the first bias voltage comparator is configured to compare the output received from the PVT effect quantifier to a first threshold value and a second threshold value to provide the first bias voltage, and the second bias voltage comparator is configured to compare the output received from the PVT effect quantifier to the first threshold value and the second threshold value to provide the second bias voltage.

A substrate bias control circuit, comprising:

• a process voltage temperature (PVT) effect transducer for responding to a PVT effect;
• a PVT effect quantifier coupled to the PVT effect transducer for quantifying the PVT effect to provide an output, the PVT effect quantifier including
• at least one counter, and
• a period generator for providing a time period for the at least one counter;
• and
• a bias controller configured to receive the output of the PVT effect quantifier and provide a first bias voltage for a substrate of a p-channel metal-oxide semiconductor (PMOS) transistor and a second bias voltage for a substrate of an n-channel metal-oxide semiconductor (NMOS) transistor,
• wherein the bias controller comprises a bias voltage lookup table that includes
• a first reference value for the output of the PVT effect quantifier,
• a first target value for the first bias voltage that corresponds to the first reference value, and
• a second target value for the second bias voltage that corresponds to the first reference value.