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US 8,552,785 B2Granted
Pulse generator
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Zhang Kuo, Jen-Hang Yang, Shang-Chih Hsieh, Chih-Chiang Chang, Osamu Takahashi, Ta-Pen Guo, Sang Hoo Dong
Life of this patent
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Abstract
A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
Claims19
A circuit, comprising:
- a first logic gate configured to receive a clock signal at a first input;
- and
- a latch disposed in a feedback loop of the first logic gate, the latch configured to output a feedback signal to a second input of the first logic gate in response to a signal output by the first logic gate and the clock signal,
- wherein the circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
1 more element
A circuit, comprising:
- a first logic gate configured to receive a clock signal at a first input;
- and
- a latch including second and third logic gates,
- the second logic gate including:
- a first input coupled to an output of the first logic gate and to a second input of the first logic gate, and
- a second input coupled to an output of the third logic gate;
- the third logic gate including:
- a first input coupled to an output of the second logic gate, and
- a second input configured to receive the clock signal,
- wherein the circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
7 more elements
Dependencies are inferred from the claim text.