Method and apparatus for determining duty cycle of a clock in a circuit using a configurable phase locked loop
AssigneeTellabs Operations, Inc.
InventorsThayl D. Zohner, Douglas A. Chandler, Jae-Hu Kim
Life of this patent
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Abstract
An embodiment of the invention discloses phase shifting a second clock signal by a phase increment with respect to a first clock signal, where the first clock signal and the second clock signal have the same periods. The first clock signal is sampled with the second clock signal, and the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state. A count of logic one samples is incremented if the sample of the first clock signal is at a logic one state. The process of phase shifting the second clock signal and sampling the first clock signal is repetitively performed to a maximum number of samples.
Claims22
A method comprising:
- phase shifting a second clock signal by a phase increment with respect to a first clock signal, wherein the first clock signal and the second clock signal have the same periods;
- sampling the first clock signal with the second clock signal, wherein the output of the sample indicates whether the sample of the first clock signal is at a logic one state or a logic zero state;
- incrementing a count of logic one samples if the sample of the first clock signal is at a logic one state;
- and
- repetitively performing the process of phase shifting the second clock signal and sampling the first clock signal.
A system comprising:
- a phase shifting circuitry configured to phase shift a second clock signal by a phase increment with respect to a first clock signal, wherein the first clock signal and the second clock signal have the same periods;
- a sampling circuitry configured to sample the first clock signal with the second clock signal, wherein the output of the sampling circuitry indicates whether the sample of the first clock signal is at a logic one state or a logic zero state;
- a counting circuitry that is configured to increment a count of logic one samples if the sample of the first clock signal is at a logic one state;
- and
- a control circuitry configured to control at least the phase shifting circuitry and the sampling circuitry to repetitively perform the process of phase shifting the second clock signal and sampling the first clock signal.
A method comprising:
- adjusting a phase of a second clock signal by a phase increment with respect to a first clock signal, wherein the second clock signal is derived from the first clock signal and has the same period as the first clock signal;
- sampling the first clock signal with the second clock signal;
- determining whether a sample of the first clock signal is a logic one or a logic zero;
- incrementing a counter if the sample is at a logic one state to update a count of logic one samples;
- determining whether the phase of the second clock signal has been adjusted a maximum number of times;
- and
- performing the process of adjusting the phase of the second clock signal and sampling the first clock signal if the phase of the second clock signal has not been adjusted by the phase increment a maximum number of times.
Dependencies are inferred from the claim text.